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1. 发明授权

US06635576B1 Method of fabricating borderless contact using graded-stair etch stop layers 有权
标题翻译：使用梯级蚀刻停止层制造无边界接触的方法
公开(公告)号：US06635576B1
公开(公告)日：2003-10-21
申请号：US09999343
申请日：2001-12-03
申请人： Meng-Chang Liu , Lin-June Wu , Kwang-Ming Lin
发明人： Meng-Chang Liu , Lin-June Wu , Kwang-Ming Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/76804 , H01L21/76832
摘要： The invention teaches the creation of borderless contact holes by using multiple layers of overlying dielectric, having different, interdependent etch rates, that function as etch stop layers for the creation of the borderless contact holes through a layer of overlying dielectric.
摘要翻译：本发明教导了通过使用具有不同的相互依赖的蚀刻速率的多层上覆电介质来形成无边界接触孔，其作为用于通过覆盖电介质层产生无边界接触孔的蚀刻停止层。

2. 发明授权

US08874981B2 Method of creating target storage layout table referenced for partitioning storage space of storage device and related electronic device and machine-readable medium 有权
标题翻译：用于分配存储设备及相关电子设备和机器可读介质的存储空间的目标存储布局表的创建方法
公开(公告)号：US08874981B2
公开(公告)日：2014-10-28
申请号：US12912751
申请日：2010-10-27
申请人： Meng-Chang Liu , Chen-Tsung Hsieh
发明人： Meng-Chang Liu , Chen-Tsung Hsieh
IPC分类号： G06F11/00 , G06F3/06
CPC分类号： G06T1/60 , G06F3/0608 , G06F3/0616 , G06F3/0644 , G06F3/0679 , G06T15/005 , G06T19/00 , G06T2200/04 , H04N13/398
摘要： An exemplary method of creating a target storage layout table referenced for partitioning a storage space of a storage device includes following steps: identifying defective storage areas in the storage space of the storage device, and accordingly generating an identification result; and creating the target storage layout table according to the identification result.
摘要翻译：用于划分存储设备的存储空间的创建目标存储布局表的示例性方法包括以下步骤：识别存储设备的存储空间中的有缺陷的存储区域，从而生成识别结果; 并根据识别结果创建目标存储布局表。

3. 发明授权

US08226425B2 Sparkless electrical connector 有权
标题翻译：无火花电气连接器
公开(公告)号：US08226425B2
公开(公告)日：2012-07-24
申请号：US12533595
申请日：2009-07-31
申请人： Shen-Yuan Chien , Meng-Chang Liu
发明人： Shen-Yuan Chien , Meng-Chang Liu
IPC分类号： H01R13/53
CPC分类号： H01R13/6616 , H01R12/721 , H01R13/113 , H01R13/53 , H01R13/652 , H01R24/22 , H01R2103/00
摘要： Methods and apparatuses supporting an electrical connection in a manner that eliminates or reduces a danger of electrical sparking are disclosed. A sparkless electrical connector has a conductor, configured to provide flow of electricity between an electrical source and a load, and a resistive element, operatively coupled to the conductor, to resist flow of electricity during a state of partial connection with the electrical source or the load. The resistive element may be not in contact with a terminal of the source or load during a state of full connection. The resistive element may be a coating of an anodized material on a pin of the conductor. The coating provides a resistance sufficient to prevent sparking during connection of the conductor and at least one of the electrical source and the load. Techniques disclosed herein benefit users and manufacturers in the areas of safety, cost, simplicity, and reliability.
摘要翻译：公开了以消除或减少电火花危险的方式支持电连接的方法和装置。无火花电连接器具有被配置为在电源和负载之间提供电流的导体和可操作地耦合到导体的电阻元件，以在与电源或部分连接的状态期间阻止电流流动加载。在完全连接的状态下，电阻元件可能不与源极或负载的端子接触。电阻元件可以是在导体的引脚上的阳极氧化材料的涂层。涂层提供足够的电阻以防止在导体和电源和负载中的至少一个连接期间发生火花。这里公开的技术在安全性，成本，简单性和可靠性方面使用户和制造商受益。

4. 发明授权

US06420248B1 Double gate oxide layer method of manufacture 有权
标题翻译：双栅氧化层制造方法
公开(公告)号：US06420248B1
公开(公告)日：2002-07-16
申请号：US09685423
申请日：2000-10-10
申请人： Meng-Chang Liu , Shea-Jue Wang
发明人： Meng-Chang Liu , Shea-Jue Wang
IPC分类号： H01L214763
CPC分类号： H01L21/823462 , H01L21/823481
摘要： A method of manufacturing a double gate oxide layer. A substrate has trenches that divide the substrate into a memory circuit region and a logic circuit region. A dielectric layer is formed on the substrate to fill the trenches. The dielectric layer of the logic region is removed, thereby exposing the substrate. An ion implantation step is performed on the substrate of the logic circuit region using a reverse tone mask. A conformal barrier layer is formed over the substrate. A spin-on layer is formed over the barrier layer. A chemical mechanical polishing step is performed to remove the in-on layer, the barrier layer, and dielectric layer outside the trenches, thereby exposing the substrate. A thermal oxidation step is performed to form a double gate oxide layer that is thicker in the logic circuit region than it is in the memory circuit region.
摘要翻译：一种制造双栅氧化层的方法。衬底具有将衬底分成存储器电路区域和逻辑电路区域的沟槽。在衬底上形成电介质层以填充沟槽。去除逻辑区域的电介质层，从而露出衬底。使用反向色调掩模在逻辑电路区域的衬底上进行离子注入步骤。在衬底上形成保形阻挡层。在阻挡层上形成旋涂层。进行化学机械抛光步骤以去除沟槽外部的内层，阻挡层和电介质层，从而暴露衬底。进行热氧化步骤以形成在逻辑电路区域比在存储器电路区域更厚的双栅氧化层。

5. 发明授权

US06358831B1 Method for forming a top interconnection level and bonding pads on an integrated circuit chip 有权
标题翻译：在集成电路芯片上形成顶部互连电平和接合焊盘的方法
公开(公告)号：US06358831B1
公开(公告)日：2002-03-19
申请号：US09261680
申请日：1999-03-03
申请人： Meng-Chang Liu , Yuan-Lung Liu
发明人： Meng-Chang Liu , Yuan-Lung Liu
IPC分类号： H01L214763
CPC分类号： H01L24/12 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/05073 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01039 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/00014
摘要： A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.
摘要翻译：描述了用于形成集成电路芯片的顶部互连电平和接合焊盘的方法。互连级别由镶嵌型工艺形成。接合焊盘放置在互连级别的布线通道的平面之上。这消除了在化学机械抛光期间，当焊盘与互连冶金在同一水平时发生的相对大的焊盘的凹陷的问题。互连布线包括较小的焊盘基部段，然后形成较大的焊盘。接合焊盘基座部分足够小，使得CMP期间的凹陷不成问题。将焊盘放置在焊盘底座上可提供更坚固的焊盘。顶级和焊盘制造程序适用于各种导电材料，包括铝，钨和铜。

6. 外观设计

USD649114S1 Interface and bezel for uninterruptible power supply 有权
标题翻译：用于不间断电源的接口和挡板
公开(公告)号：USD649114S1
公开(公告)日：2011-11-22
申请号：US29393939
申请日：2011-06-10
申请人： Kyle David Brookshire , Meng-Chang Liu , James Edward Briggs
设计人： Kyle David Brookshire , Meng-Chang Liu , James Edward Briggs

7. 外观设计

USD648676S1 A/V uninterruptible power supply 有权
标题翻译： A / V不间断电源
公开(公告)号：USD648676S1
公开(公告)日：2011-11-15
申请号：US29377415
申请日：2010-10-21
申请人： Kyle Brookshire , Meng-Chang Liu , Daniel R. Armstrong
设计人： Kyle Brookshire , Meng-Chang Liu , Daniel R. Armstrong

8. 外观设计

USD626066S1 Uninterruptible power supply 有权
标题翻译：不间断电源供应
公开(公告)号：USD626066S1
公开(公告)日：2010-10-26
申请号：US29360582
申请日：2010-04-28
申请人： Meng-Chang Liu , Kyle Brookshire , Karl D. Langmuir
设计人： Meng-Chang Liu , Kyle Brookshire , Karl D. Langmuir

9. 外观设计

USD601957S1 Removeable user interface module for an uninterruptible power supply 有权
标题翻译：用于不间断电源的可拆卸用户界面模块
公开(公告)号：USD601957S1
公开(公告)日：2009-10-13
申请号：US29334545
申请日：2009-03-27
申请人： Arthur Joseph Blake, Jr. , Kyle Brookshire , Meng-Chang Liu , Brian Peter McKenna
设计人： Arthur Joseph Blake, Jr. , Kyle Brookshire , Meng-Chang Liu , Brian Peter McKenna

10. 发明授权

US06485654B1 Method of fabricating self-aligned contacts 有权
标题翻译：制造自对准触点的方法
公开(公告)号：US06485654B1
公开(公告)日：2002-11-26
申请号：US09672548
申请日：2000-09-28
申请人： Meng-Chang Liu , Shea-Jue Wang
发明人： Meng-Chang Liu , Shea-Jue Wang
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L27/10873 , H01L27/10888 , Y10S438/947
摘要： A process for producing a self-aligned contact comprises the steps of forming leads on a substrate, forming an etching stop layer on the leads by depositing, then forming a sacrificed oxide layer; after the structure of the leads is defined, a spacer is formed on both sides of the structure; a sacrificed oxide layer is formed, allowing the spacer to protrude in the form of horn. Next, a dielectric layer having a flat upper surface is deposited on the substrate and the structure of leads, a contact hole being formed between the leads so as to connect the substrate, a conductive material being filled in the contact hole to form a plug.
摘要翻译：用于制造自对准接触的方法包括以下步骤：在衬底上形成引线，通过沉积形成牺牲氧化物层，在引线上形成蚀刻停止层; 在限定了引线的结构之后，在结构的两侧形成间隔物; 形成牺牲的氧化物层，允许间隔件以喇叭形式突出。接下来，将具有平坦的上表面的电介质层沉积在基板上，并且引线的结构，在引线之间形成接触孔，以便连接基板，填充在接触孔中的导电材料形成插头。

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