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    • 3. 发明授权
    • Dual ECC decoder
    • 双ECC解码器
    • US08429498B1
    • 2013-04-23
    • US12728289
    • 2010-03-22
    • Micha AnholtNaftali SommerRonen DarUri PerlmutterTal Inbar
    • Micha AnholtNaftali SommerRonen DarUri PerlmutterTal Inbar
    • G11C29/00
    • G06F11/1048G11C2029/0411
    • A decoding apparatus includes a decoder and a control unit. The decoder includes circuitry that is configured to decode an Error Correction Code (ECC) by operating in one of a first operational mode having a first power consumption, and a second operational mode, in which at least part of the circuitry that is active during the first operational mode is deactivated and which has a second power consumption that is lower than the first power consumption. The control unit is configured to evaluate a criterion with respect to an input code word, to select one of the first and second operational modes responsively to the criterion, and to invoke the decoder to decode the input code word using the selected operational mode.
    • 解码装置包括解码器和控制单元。 解码器包括经配置以通过以具有第一功率消耗的第一操作模式和第二操作模式之一进行操作来解码错误校正码(ECC)的电路,其中在该期间内的有效电路的至少一部分 第一操作模式被禁用并且具有低于第一功率消耗的第二功率消耗。 控制单元被配置为评估关于输入代码字的标准,以响应于该标准选择第一和第二操作模式中的一个,并且使用所选择的操作模式调用解码器对输入的代码字进行解码。