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    • 1. 发明申请
    • Double flip semiconductor device and method for fabrication
    • 双层半导体器件及其制造方法
    • US20080197369A1
    • 2008-08-21
    • US11708990
    • 2007-02-20
    • Max BatresJames IbbetsonNicholas W. MedendorpJulio A. Garceran
    • Max BatresJames IbbetsonNicholas W. MedendorpJulio A. Garceran
    • H01L33/00H01L21/00
    • H01L33/0079H01L33/22H01L33/405H01L33/44
    • A double flip-chip semiconductor device formed by a double flip fabrication process. Epitaxial layers are grown on a substrate in the normal fashion with the n-type layers grown first and the p-type layers grown subsequently. The chip is flipped a first time and mounted to a sacrificial layer. The original substrate is removed, exposing the n-type layer, and various additional layers and treatments are added to the device. Because the n-type layer is exposed during fabrication, the layer may be processed in various ways including adding a reflective element, texturing the surface or adding microstructures to the layer to improve light extraction. The chip is flipped a second time and mounted to a support element. The sacrificial layer is then removed and additional layers and treatment are added to the device. The finished device features a configuration in which the layers maintain the same orientation with respect to the support element that they had with the original substrate on which they were grown. Processing the n-type layers, rather than the p-type layers as in a single flip process, provides greater design flexibility when selecting features to add to the device. Thus, previously unavailable processes and reflective elements may be utilized, enhancing the external quantum efficiency of the device.
    • 通过双层翻转制造工艺形成的双倒装芯片半导体器件。 以正常方式在衬底上生长外延层,其中首先生长n型层,随后生长p型层。 芯片首次翻转并安装到牺牲层。 去除原始基底,暴露n型层,并将各种附加层和处理添加到该装置中。 因为n型层在制造过程中被曝光,所以该层可以以各种方式加工,包括添加反射元件,使表面纹理化或者向层中添加微结构以改善光提取。 芯片第二次翻转并安装在支撑元件上。 然后去除牺牲层,并向设备添加附加层和处理。 完成的装置具有这样的构造,其中层相对于它们与其生长在其上的原始基底所具有的支撑元件保持相同的取向。 在单次翻转过程中处理n型层而不是p型层,在选择要添加到设备中的特征时,提供更大的设计灵活性。 因此,可以利用先前不可用的处理和反射元件,增强器件的外部量子效率。