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1. 发明申请

US20130308893A1 INTEGRATED DRIVER AND RELATED METHOD 有权
标题翻译：集成驱动器及相关方法
公开(公告)号：US20130308893A1
公开(公告)日：2013-11-21
申请号：US13989488
申请日：2011-12-01
申请人： Maurizio Zuffada , Massimo Pozzoni , Angelo Contini
发明人： Maurizio Zuffada , Massimo Pozzoni , Angelo Contini
IPC分类号： H03F3/217 , H03F3/45 , G02F1/01 , H03F1/22
CPC分类号： G02F1/0121 , G02B6/1225 , G02B2006/12142 , G02B2006/12145 , G02F1/0327 , G02F1/225 , G02F2001/212 , H03F1/22 , H03F1/223 , H03F3/2171 , H03F3/245 , H03F3/3001 , H03F3/45076 , H03F3/45179 , H03F2200/45 , H03F2200/516 , H03F2203/30099 , H03F2203/30132 , H03K19/018528 , H04B10/532 , H04B10/616
摘要： A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).
摘要翻译：驱动器电路可以包括第一节点（VA）和第一电路，用于在第一电源电压（Vdd1）和地之间的驱动器切换期间在第一节点（VA）上产生输入信号（VIN）的反相副本，反转副本具有基于大于第一电源电压（Vdd1）的参考电压（Vref）的阈值电压值。驱动器电路可以包括由参考电压（Vref）控制并耦合在第二电源电压（Vdd2）和第一节点之间的共源共栅级（M3），延迟电路（D）以产生延迟复制输入信号（VIN），放大器和开关网络（M5，M6），用于将有源负载晶体管（M9）的控制端子耦合到参考电压（Vref）中的一个或接地，基于输入信号（VIN）。

2. 发明授权

US08253473B2 Integrated circuit of an integrator with enhanced stability and related stabilization method 有权
标题翻译：具有增强稳定性和相关稳定方法的积分器集成电路
公开(公告)号：US08253473B2
公开(公告)日：2012-08-28
申请号：US12893908
申请日：2010-09-29
申请人： Maurizio Zuffada , Massimo Pozzoni
发明人： Maurizio Zuffada , Massimo Pozzoni
IPC分类号： G06F7/64 , G06G7/18 , G06G7/19
CPC分类号： H03H11/0422 , Y10T29/49124
摘要： An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.
摘要翻译：集成电路积分器包括具有基于第一控制信号可调节的增益的第一跨导放大器，并且接收要被滤波的信号作为输入，并产生相应的放大信号作为输出。第一跨导放大器包括R-C输出电路，用于根据放大的信号对分量进行滤波，并且输出电阻可根据第二控制信号进行调节。第二跨导放大器与第一跨导放大器匹配，并且具有基于第一控制信号可调节的增益，以及基于第二控制信号可调整的匹配输出电阻。电路被配置为迫使参考电流通过匹配的输出电阻。误差校正电路耦合到第二跨导放大器，并且被配置为产生第二控制信号，以便使第二跨导放大器的输出上的电压保持恒定。

3. 发明申请

US20110080218A1 INTEGRATED CIRCUIT OF AN INTEGRATOR WITH ENHANCED STABILITY AND RELATED STABILIZATION METHOD 有权
标题翻译：具有增强稳定性和相关稳定方法的集成电路的集成电路
公开(公告)号：US20110080218A1
公开(公告)日：2011-04-07
申请号：US12893908
申请日：2010-09-29
申请人： Maurizio ZUFFADA , Massimo Pozzoni
发明人： Maurizio ZUFFADA , Massimo Pozzoni
IPC分类号： H03G3/00
CPC分类号： H03H11/0422 , Y10T29/49124
摘要： An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.
摘要翻译：集成电路积分器包括具有基于第一控制信号可调节的增益的第一跨导放大器，并且接收要被滤波的信号作为输入，并产生相应的放大信号作为输出。第一跨导放大器包括R-C输出电路，用于根据放大的信号对分量进行滤波，并且输出电阻可根据第二控制信号进行调节。第二跨导放大器与第一跨导放大器匹配，并且具有基于第一控制信号可调节的增益，以及基于第二控制信号可调整的匹配输出电阻。电路被配置为迫使参考电流通过匹配的输出电阻。误差校正电路耦合到第二跨导放大器，并且被配置为产生第二控制信号，以便使第二跨导放大器的输出上的电压保持恒定。

4. 发明授权

US09099965B2 Integrated driver and related method 有权
标题翻译：集成驱动及相关方法
公开(公告)号：US09099965B2
公开(公告)日：2015-08-04
申请号：US13989488
申请日：2011-12-01
申请人： Maurizio Zuffada , Massimo Pozzoni , Angelo Contini
发明人： Maurizio Zuffada , Massimo Pozzoni , Angelo Contini
IPC分类号： G02B6/00 , G02F1/01 , H03F1/22 , H03F3/217 , H03F3/24 , H03F3/30 , H03F3/45 , H03K19/0185 , H04B10/532 , H04B10/61 , G02F1/03 , G02F1/225
CPC分类号： G02F1/0121 , G02B6/1225 , G02B2006/12142 , G02B2006/12145 , G02F1/0327 , G02F1/225 , G02F2001/212 , H03F1/22 , H03F1/223 , H03F3/2171 , H03F3/245 , H03F3/3001 , H03F3/45076 , H03F3/45179 , H03F2200/45 , H03F2200/516 , H03F2203/30099 , H03F2203/30132 , H03K19/018528 , H04B10/532 , H04B10/616
摘要： A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).
摘要翻译：驱动器电路可以包括第一节点（VA）和第一电路，用于在第一电源电压（Vdd1）和地之间的驱动器切换期间在第一节点（VA）上产生输入信号（VIN）的反相副本，反转副本具有基于大于第一电源电压（Vdd1）的参考电压（Vref）的阈值电压值。驱动器电路可以包括由参考电压（Vref）控制并耦合在第二电源电压（Vdd2）和第一节点之间的共源共栅级（M3），延迟电路（D）以产生延迟复制输入信号（VIN），放大器和开关网络（M5，M6），用于将有源负载晶体管（M9）的控制端子耦合到参考电压（Vref）中的一个或接地，基于输入信号（VIN）。

5. 发明授权

US08373488B2 Integrated circuit of an integrator with enhanced stability and related stabilization method 有权
标题翻译：具有增强稳定性和相关稳定方法的积分器集成电路
公开(公告)号：US08373488B2
公开(公告)日：2013-02-12
申请号：US13561355
申请日：2012-07-30
申请人： Maurizio Zuffada , Massimo Pozzoni
发明人： Maurizio Zuffada , Massimo Pozzoni
IPC分类号： G06F7/64 , G06G7/18 , G06G7/19
CPC分类号： H03H11/0422 , Y10T29/49124
摘要： An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.
摘要翻译：集成电路积分器包括具有基于第一控制信号可调节的增益的第一跨导放大器，并且接收要被滤波的信号作为输入，并产生相应的放大信号作为输出。第一跨导放大器包括R-C输出电路，用于根据放大的信号对分量进行滤波，并且输出电阻可根据第二控制信号进行调节。第二跨导放大器与第一跨导放大器匹配，并且具有基于第一控制信号可调节的增益，以及基于第二控制信号可调整的匹配输出电阻。电路被配置为迫使参考电流通过匹配的输出电阻。误差校正电路耦合到第二跨导放大器，并且被配置为产生第二控制信号，以便使第二跨导放大器的输出上的电压保持恒定。

6. 发明申请

US20050111589A1 Method and circuit for sensing the transition density of a signal and variable gain phase detecting method and device 审中-公开
标题翻译：用于感测信号转换密度的方法和电路以及可变增益相位检测方法和装置
公开(公告)号：US20050111589A1
公开(公告)日：2005-05-26
申请号：US10837508
申请日：2004-04-30
申请人： Francesco Centurelli , Massimo Pozzoni , Giuseppe Scotti , Alessandro Trifiletti
发明人： Francesco Centurelli , Massimo Pozzoni , Giuseppe Scotti , Alessandro Trifiletti
IPC分类号： H03D13/00 , H03L7/085 , H04L7/033 , H04L27/14
CPC分类号： H03L7/085 , H03D13/00 , H04L7/033
摘要： A linear phase detector has a variable gain that is regulated as a function of the monitored transition density of the input signal. The transition density is sensed by a circuit that generates a signal corresponding to a time averaged common mode component of the differential signal output by an output stage of the phase detector.
摘要翻译：线性相位检测器具有可变增益，该可变增益作为监视的输入信号的转换密度的函数被调节。转移密度由生成与由相位检测器的输出级输出的差分信号的时间平均共模分量相对应的信号的电路感测。

7. 发明授权

US6060758A Method and device for suppressing parasitic effects in a junction-isolation integrated circuit 失效
标题翻译：用于抑制结隔离集成电路中的寄生效应的方法和装置
公开(公告)号：US6060758A
公开(公告)日：2000-05-09
申请号：US976863
申请日：1997-11-24
申请人： Enrico Maria Ravanelli , Massimo Pozzoni , Giorgio Pedrazzini , Giulio Ricotti
发明人： Enrico Maria Ravanelli , Massimo Pozzoni , Giorgio Pedrazzini , Giulio Ricotti
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/088 , H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0248 , H01L27/088
摘要： A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.
摘要翻译：抑制方法被应用于形成在具有至少一个具有结隔离的n型材料的区域的p型材料的衬底上的集成电路，在衬底的正面上的第一电接触，在衬底的正面上的第二电接触 n型区域和连接到集成电路的基准（地））端子的衬底的背面上的第三电接触。为了避免由于集成电路的某些工作条件下的寄生双极晶体管的导通而导致衬底中的电流，该方法提供了监视第二接触点的电位以检测该电位是否偏离参考端子的（接地）电位大于预定阈值的量。如果发生这种情况，则首先接触第二个触点的电位，否则它们保持在参考端子的（接地）电位。还描述了利用该方法的装置和集成电路。

8. 发明授权

US06248616B1 Method for suppressing parasitic effects in a junction-isolation integrated circuit 有权
标题翻译：用于抑制结隔离集成电路中的寄生效应的方法
公开(公告)号：US06248616B1
公开(公告)日：2001-06-19
申请号：US09491326
申请日：2000-01-26
申请人： Enrico Maria Ravanelli , Massimo Pozzoni , Giorgio Pedrazzini , Giulio Ricotti
发明人： Enrico Maria Ravanelli , Massimo Pozzoni , Giorgio Pedrazzini , Giulio Ricotti
IPC分类号： H01L21332
CPC分类号： H01L27/0248 , H01L27/088
摘要： A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.
摘要翻译：抑制方法被应用于形成在具有至少一个具有结隔离的n型材料的区域的p型材料的衬底上的集成电路，在衬底的正面上的第一电接触，在衬底的正面上的第二电接触 n型区域和连接到集成电路的基准（地））端子的衬底的背面上的第三电接触。为了避免由于集成电路的某些工作条件下的寄生双极晶体管的导通而导致衬底中的电流，该方法提供了监视第二接触点的电位以检测该电位是否偏离参考端子的（接地）电位大于预定阈值的量。如果发生这种情况，则首先接触第二个触点的电位，否则它们保持在参考端子的（接地）电位。还描述了利用该方法的装置和集成电路。

9. 发明授权

US08315300B2 Enhancement of transition region equalization in a decision feedback equalizer 有权
标题翻译：在决策反馈均衡器中增强过渡区域均衡
公开(公告)号：US08315300B2
公开(公告)日：2012-11-20
申请号：US12581554
申请日：2009-10-19
申请人： Massimo Pozzoni
发明人： Massimo Pozzoni
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03063 , H04L25/0307 , H04L2025/03356 , H04L2025/03579
摘要： A decision feedback equalizer includes an input path for receiving a bitstream with inter-symbol interference, and a feedback signal path is coupled to the input path for correcting a sampled value of an incoming bit of the bitstream based on inter-symbol interference of a preceding bit. The feedback signal path includes a controllable delay circuit for receiving the preceding bit. A feedback path controller is coupled to the controllable delay circuit to regulate a delay introduced to the preceding bit. The delay is a function of an accumulated value of data of early-late events of a sampling instant of the bitstream for different data pulse patterns.
摘要翻译：判决反馈均衡器包括用于接收具有符号间干扰的比特流的输入路径，并且反馈信号路径被耦合到输入路径，用于基于前一个的符号间干扰校正比特流的输入比特的采样值位。反馈信号路径包括用于接收前一位的可控延迟电路。反馈路径控制器耦合到可控延迟电路以调节引入到前一位的延迟。该延迟是针对不同数据脉冲模式的比特流的采样时刻的早期事件的数据的累积值的函数。

10. 发明申请

US20100103998A1 DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY 有权
标题翻译：具有最小校正延迟的决策反馈均衡方案
公开(公告)号：US20100103998A1
公开(公告)日：2010-04-29
申请号：US12419347
申请日：2009-04-07
申请人： SIMONE ERBA , Massimo Pozzoni
发明人： SIMONE ERBA , Massimo Pozzoni
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03063 , H04L25/0307 , H04L2025/03356 , H04L2025/03579
摘要： A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.
摘要翻译：判决反馈均衡器包括校正电路，用于基于至少一个先前位的符号间干扰来校正输入位的采样值，并产生接收位。校正电路包括第一多路复用器和耦合到其上的第一对锁存器。第一多路复用器由时钟信号控制，以产生代表第一校正系数的符号的数字电平，以便从用于删除符号间干扰的输入位的采样值中减去。第一对锁存器作为输入接收接收的位，并且通过时钟信号相位对准时钟，以在时钟信号的相应有效相位期间产生接收位的相应锁存副本。相应的锁存副本被输入到第一多路复用器。

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