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1. 发明授权

US08471236B2 Flat lower bottom electrode for phase change memory cell 失效
标题翻译：用于相变存储单元的平底下电极
公开(公告)号：US08471236B2
公开(公告)日：2013-06-25
申请号：US13550091
申请日：2012-07-16
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

2. 发明授权

US08283650B2 Flat lower bottom electrode for phase change memory cell 有权
标题翻译：用于相变存储单元的平底下电极
公开(公告)号：US08283650B2
公开(公告)日：2012-10-09
申请号：US12550048
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

3. 发明授权

US08728859B2 Small footprint phase change memory cell 有权
标题翻译：小尺寸相变存储单元
公开(公告)号：US08728859B2
公开(公告)日：2014-05-20
申请号：US12855079
申请日：2010-08-12
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung
IPC分类号： H01L21/00 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
摘要翻译：所公开的示例性实施例是用于制造相变存储单元的方法。该方法包括在绝缘衬底内形成非亚光刻通孔。绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。亚光刻孔填充有导电非相变材料。此外，相变材料沉积在非亚光刻通孔内。

4. 发明申请

US20110049462A1 FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL 有权
标题翻译：平底下电极用于相变记忆体
公开(公告)号：US20110049462A1
公开(公告)日：2011-03-03
申请号：US12550048
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/768 , H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

5. 发明申请

US20120280197A1 FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL 失效
标题翻译：平底下电极用于相变记忆体
公开(公告)号：US20120280197A1
公开(公告)日：2012-11-08
申请号：US13550091
申请日：2012-07-16
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

6. 发明申请

US20120037877A1 ONE-MASK PHASE CHANGE MEMORY PROCESS INTEGRATION 有权
标题翻译：单掩模相变记忆过程集成
公开(公告)号：US20120037877A1
公开(公告)日：2012-02-16
申请号：US12855079
申请日：2010-08-12
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung
IPC分类号： H01L45/00 , H01L29/40 , H01L21/02
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
摘要翻译：所公开的示例性实施例是用于制造相变存储单元的方法。该方法包括在绝缘衬底内形成非亚光刻通孔。绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。亚光刻孔填充有导电非相变材料。此外，相变材料沉积在非亚光刻通孔内。

7. 发明授权

US08310864B2 Self-aligned bit line under word line memory array 有权
标题翻译：字线内存阵列下的自对准位线
公开(公告)号：US08310864B2
公开(公告)日：2012-11-13
申请号：US12815680
申请日：2010-06-15
申请人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
摘要翻译：描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字线条。对于其中垂直晶体管是场效应晶体管的实施例，字线提供周围的栅极结构。存储元件形成为与垂直晶体管电连通。提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。

8. 发明授权

US07935564B2 Self-converging bottom electrode ring 失效
标题翻译：自收敛底电极环
公开(公告)号：US07935564B2
公开(公告)日：2011-05-03
申请号：US12036372
申请日：2008-02-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683 , Y10S438/90
摘要： A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.
摘要翻译：一种包括自会聚底电极环的方法和存储单元。该方法包括在衬底上形成台阶间隔物，顶部绝缘层，中间绝缘层和底部绝缘层。该方法包括在顶部绝缘层和中间绝缘层内形成台阶间隔物。台阶垫片尺寸易于控制。该方法还包括在步骤间隔物作为掩模的底部绝缘层中形成通道。所述方法包括在所述通道内形成底部电极环，所述通道包括所述通道内的杯形外部导电层，并且在所述杯形外部导电层内形成内部绝缘层。该方法包括在底部电极环上方形成相变层和在底部电极环上方形成顶部电极。

9. 发明申请

US20090268507A1 PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURE 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090268507A1
公开(公告)日：2009-10-29
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译：公开了一种相变存储器控制环下电极。下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层。

10. 发明申请

US20080164453A1 UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION 审中-公开
标题翻译：用于PCRAM应用的均匀尺寸尺寸孔
公开(公告)号：US20080164453A1
公开(公告)日：2008-07-10
申请号：US11620671
申请日：2007-01-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Chung H. Lam , Hsiang-Lan Lung , Eirc A. Joseph , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Chung H. Lam , Hsiang-Lan Lung , Eirc A. Joseph , Alejandro G. Schrott
IPC分类号： H01L47/00 , H01L21/28
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.
摘要翻译：存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层层。在中间绝缘层上方的绝缘层中限定通孔。创建一个通道用于用牺牲隔离物进行蚀刻。在中间绝缘层中限定孔。除去中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。在相变材料上形成上电极。

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