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1. 发明授权

US07203811B2 Non-fenced list DMA command mechanism 有权
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US07203811B2
公开(公告)日：2007-04-10
申请号：US10631542
申请日：2003-07-31
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G00F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的方法和装置。列表DMA命令涉及系统存储器的有效地址（EA）。系统中至少有一个处理器具有本地存储。列表DMA命令在DMA队列（DMAQ）中排队。列表元素从本地存储器获取到DMAQ。从DMAQ读取列表DMA命令。为列表元素发出总线请求。如果总线请求是最后一个请求，则确定当前列表元素是否是最后一个列表元素。如果当前列表元素不是最后的列表元素，则确定当前列表元素是否被围栏。如果当前列表元素没有围栏，则无论所有未完成的请求是否完成，都会获取下一个列表元素。

2. 发明授权

US07512722B2 Method for completing a plurality of chained list DMA commands that include a fenced list DMA command element 失效
标题翻译：用于完成包括围栏列表DMA命令元素的多个链表DMA命令的方法
公开(公告)号：US07512722B2
公开(公告)日：2009-03-31
申请号：US10631541
申请日：2003-07-31
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28 , G06F9/46
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的方法，装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

3. 发明授权

US07877523B2 Apparatus, computer program product, and system for completing a plurality of chained list DMA commands that include a fenced list DMA command element 有权
标题翻译：装置，计算机程序产品和用于完成包括围栏列表DMA命令元素的多个链表DMA命令的系统
公开(公告)号：US07877523B2
公开(公告)日：2011-01-25
申请号：US12331733
申请日：2008-12-10
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

4. 发明申请

US20090094388A1 DMA Completion Mechanism 有权
标题翻译： DMA完成机制
公开(公告)号：US20090094388A1
公开(公告)日：2009-04-09
申请号：US12331733
申请日：2008-12-10
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

5. 发明授权

US07444435B2 Non-fenced list DMA command mechanism 失效
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US07444435B2
公开(公告)日：2008-10-28
申请号：US11686083
申请日：2007-03-14
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F3/00 , G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ. Each list element comprises a stall bit indicating whether the list element is fenced and a DMA completion logic (DCL) is coupled to the at least one processor, the issue logic, and the RIL, and configured to indicate completion of all outstanding bus requests relating to the list element.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的DMA控制器（DMAC）。计算机系统具有至少一个处理器和系统存储器，该列表DMA命令涉及系统存储器的有效地址（EA），并且该至少一个处理器具有本地存储器。 DMAC包括耦合到本地存储器的DMA命令队列（DMAQ），并配置为从本地存储器接收列表DMA命令并使列表DMA命令入队。问题逻辑被耦合到DMAQ并被配置为向DMAQ发出问题请求。请求接口逻辑（RIL）耦合到DMAQ并被配置为基于发出请求读取列表DMA命令。 RIL还耦合到本地存储器并且被配置为向本地存储器发送提取请求以发起从本地存储器向DMAQ获取列表DMA命令的列表元素。每个列表元素包括停止比特，指示该列表元素是否被围栏，并且一个DMA完成逻辑（DCL）被耦合到该至少一个处理器，该发行逻辑和该RIL，并被配置为指示所有未完成的总线请求的完成到列表元素。

6. 发明申请

US20110246695A1 CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS 失效
标题翻译：控制带宽预留方法和装置
公开(公告)号：US20110246695A1
公开(公告)日：2011-10-06
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： G06F12/00
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

7. 发明授权

US08611368B2 Controlling bandwidth reservations method and apparatus 失效
公开(公告)号：US08611368B2
公开(公告)日：2013-12-17
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/43 , H04L12/28
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

8. 发明申请

US20070083680A1 System and method for improved DMAC translation mechanism 有权
标题翻译：改进DMAC翻译机制的系统和方法
公开(公告)号：US20070083680A1
公开(公告)日：2007-04-12
申请号：US11246585
申请日：2005-10-07
申请人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
发明人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
IPC分类号： G06F13/28
CPC分类号： G06F12/1081 , G06F13/28
摘要： A system and method for improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.
摘要翻译：提出了一种用于改进DMAC转换机制的系统和方法。 DMA命令根据DMA命令的传输大小和计算机系统一次传输的数据量“展开”。对于第一个DMA请求，DMA队列请求内存管理单元执行地址转换。 DMA队列从MMU接收实际页码，并且在随后的发布请求中，DMA队列向总线接口单元提供实际页号，而不访问MMU，直到传输跨进下一页。在每个DMA请求之后，滚动逻辑会递减DMA命令的传输大小，确定是否已经达到新的页面，确定DMA命令是否完成，并将后续的DMA请求的回写信息发送到DMA队列。

9. 发明授权

US07644198B2 DMAC translation mechanism 有权
标题翻译： DMAC翻译机制
公开(公告)号：US07644198B2
公开(公告)日：2010-01-05
申请号：US11246585
申请日：2005-10-07
申请人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
发明人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F12/1081 , G06F13/28
摘要： An improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.
摘要翻译：提出了改进的DMAC翻译机制。 DMA命令根据DMA命令的传输大小和计算机系统一次传输的数据量“展开”。对于第一个DMA请求，DMA队列请求内存管理单元执行地址转换。 DMA队列从MMU接收实际页码，并且在随后的发布请求中，DMA队列向总线接口单元提供实际页号，而不访问MMU，直到传输跨进下一页。在每个DMA请求之后，滚动逻辑会递减DMA命令的传输大小，确定是否已经达到新的页面，确定DMA命令是否完成，并将后续的DMA请求的回写信息发送到DMA队列。

10. 发明授权

US08483227B2 Controlling bandwidth reservations method and apparatus 有权
标题翻译：控制带宽预留方法和装置
公开(公告)号：US08483227B2
公开(公告)日：2013-07-09
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/56
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

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