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1. 发明授权

US08173504B2 Method of fabricating gate electrode using a treated hard mask 有权
标题翻译：使用经处理的硬掩模制造栅电极的方法
公开(公告)号：US08173504B2
公开(公告)日：2012-05-08
申请号：US12758491
申请日：2010-04-12
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Hui Ouyang , Chi-Ming Yang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Hui Ouyang , Chi-Ming Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/4916 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.
摘要翻译：公开了一种用于制造集成器件的方法。在基板上设置多晶硅栅电极层。在一个实施例中，在多晶硅栅极电极层上提供处理以在栅电极层中引入物质并在其中形成电中和部分。然后，将具有有限厚度的硬掩模层施加在经处理的多晶硅栅极电极层上。因此，在将硬掩模层和经处理的多晶硅栅电极图案化之后，在栅极结构上对基板进行倾斜角度离子注入。

2. 发明授权

US08415254B2 Method for removing dummy poly in a gate last process 有权
标题翻译：在门最后一个过程中去除虚拟多边形的方法
公开(公告)号：US08415254B2
公开(公告)日：2013-04-09
申请号：US12275082
申请日：2008-11-20
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
IPC分类号： H01L21/302
CPC分类号： H01L21/32134 , H01L21/02071 , H01L21/28035 , H01L21/823828 , H01L21/82385 , H01L27/11 , H01L29/66583
摘要： A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
摘要翻译：提供了制造半导体器件的方法。该方法包括通过循环从位于衬底上的栅极结构去除硅材料，包括：蚀刻硅材料以除去其中的一部分，其中衬底以旋转速率纺丝，向衬底施加清洁剂，并干燥基材; 并重复该循环，其中随后的循环包括用于在蚀刻期间旋转衬底的随后旋转速率，并且其中随后的旋转速率不超过先前循环的旋转速率。

3. 发明申请

US20100124823A1 NOVEL METHOD FOR REMOVING DUMMY POLY IN A GATE LAST PROCESS 有权
标题翻译：用于在门过程中去除多余聚合物的新方法
公开(公告)号：US20100124823A1
公开(公告)日：2010-05-20
申请号：US12275082
申请日：2008-11-20
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
IPC分类号： H01L21/302 , H01L21/71
CPC分类号： H01L21/32134 , H01L21/02071 , H01L21/28035 , H01L21/823828 , H01L21/82385 , H01L27/11 , H01L29/66583
摘要： A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
摘要翻译：提供了制造半导体器件的方法。该方法包括通过循环从位于衬底上的栅极结构去除硅材料，包括：蚀刻硅材料以除去其中的一部分，其中衬底以旋转速率纺丝，向衬底施加清洁剂，并干燥基材; 并重复该循环，其中随后的循环包括用于在蚀刻期间旋转衬底的随后旋转速率，并且其中随后的旋转速率不超过先前循环的旋转速率。

4. 发明申请

US20120049247A1 MODIFIED PROFILE GATE STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FORMING THEREOF 有权
标题翻译：半导体器件的改性型材结构及其形成方法
公开(公告)号：US20120049247A1
公开(公告)日：2012-03-01
申请号：US12872642
申请日：2010-08-31
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/6656
摘要： A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.
摘要翻译：示出了制造半导体器件的方法。改进的型材开口形成在基板上。改进的型材开口包括靠近基材的表面的第一宽度和与基材相对的第二宽度。第二宽度大于第一宽度。通过用导电材料填充改性型材开口形成金属栅电极。还描述了一种半导体器件，该器件具有第一宽度和第二宽度不同的金属栅极结构。

5. 发明授权

US08329546B2 Modified profile gate structure for semiconductor device and methods of forming thereof 有权
标题翻译：用于半导体器件的改性型门结构及其形成方法
公开(公告)号：US08329546B2
公开(公告)日：2012-12-11
申请号：US12872642
申请日：2010-08-31
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
IPC分类号： H01L21/336 , H01L21/3213
CPC分类号： H01L29/66545 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/6656
摘要： A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.
摘要翻译：示出了制造半导体器件的方法。改进的型材开口形成在基板上。改进的型材开口包括靠近基材的表面的第一宽度和与基材相对的第二宽度。第二宽度大于第一宽度。通过用导电材料填充改性型材开口形成金属栅电极。还描述了一种半导体器件，该器件具有第一宽度和第二宽度不同的金属栅极结构。

6. 发明授权

US08361855B2 Method for fabricating a gate structure 有权
标题翻译：栅极结构的制造方法
公开(公告)号：US08361855B2
公开(公告)日：2013-01-29
申请号：US13252642
申请日：2011-10-04
申请人： Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Ouyang Hui
发明人： Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Ouyang Hui
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/2822 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：制造栅极结构的方法包括：在衬底上依次沉积和图案化虚拟氧化物层和伪栅极电极层; 用含氮介电层和层间电介质层包围虚拟氧化物层和虚拟栅极电极层; 去除所述伪栅电极层; 通过在第一温度将所述虚拟氧化物层的表面暴露于包含NH 3和含氟化合物的蒸气混合物中来除去所述虚拟氧化物层; 将基板加热到第二温度以在含氮介电层中形成开口; 沉积栅极电介质; 并沉积栅电极。

7. 发明授权

US08048733B2 Method for fabricating a gate structure 有权
标题翻译：栅极结构的制造方法
公开(公告)号：US08048733B2
公开(公告)日：2011-11-01
申请号：US12757295
申请日：2010-04-09
申请人： Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Ouyang Hui
发明人： Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Ouyang Hui
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/2822 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：制造栅极结构的方法包括：在衬底上依次沉积和图案化虚拟氧化物层和伪栅极电极层; 用含氮介电层和层间电介质层包围虚拟氧化物层和虚拟栅极电极层; 去除所述伪栅电极层; 通过在第一温度将所述虚拟氧化物层的表面暴露于包含NH 3和含氟化合物的蒸气混合物中来除去所述虚拟氧化物层; 将基板加热到第二温度以在含氮介电层中形成开口; 沉积栅极电介质; 并沉积栅电极。

8. 发明授权

US09349657B2 Fabrication methods of integrated semiconductor structure 有权
标题翻译：集成半导体结构的制作方法
公开(公告)号：US09349657B2
公开(公告)日：2016-05-24
申请号：US13162813
申请日：2011-06-17
申请人： Sheng-Hsiung Wang , Hsien-Chin Lin , Yuan-Ching Peng , Chia-Pin Lin , Fan-Yi Hsu , Ya-Jou Hsieh
发明人： Sheng-Hsiung Wang , Hsien-Chin Lin , Yuan-Ching Peng , Chia-Pin Lin , Fan-Yi Hsu , Ya-Jou Hsieh
IPC分类号： C23C16/24 , H01L21/20 , H01L21/36 , H01L21/8238 , H01L29/66 , H01L21/3205 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/66545
摘要： A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.
摘要翻译：一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。在第一区域和第二区域中的衬底上形成介电层。在电介质层上形成牺牲栅极层。对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极堆叠。在第一和第二区域内的栅堆叠内形成ILD层。去除第一和第二区域中的牺牲栅极层。在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

9. 发明授权

US6025588A Optical analog potentiometer 失效
标题翻译：光模拟电位器
公开(公告)号：US6025588A
公开(公告)日：2000-02-15
申请号：US157269
申请日：1998-09-21
申请人： Fan-Yi Hsu
发明人： Fan-Yi Hsu
IPC分类号： G01D5/32 , G01D5/36 , H01L31/16 , G01D5/34 , G01J1/32
CPC分类号： G01D5/32 , G01D5/36 , H01L31/164
摘要： A potentiometer includes a shaft, a base including a printed circuit board on which are fixedly mounted a light emitter and a light receiver arranged opposite to and spaced from the light emitter, the light emitter being supplied with steady voltage to emit light and provide working voltage to the light receiver, a circular seat formed with an opening and fixedly mounted on an upper end of the shaft, a plastic film arranged on an outer edge of the opening and disposed between the light emitter and the light receiver, the plastic film being provided two end portions which are opaque and an intermediate portion which decreases in transparency from one side to another side thereof, and a cover fixedly mounted on the base to enclose the circular seat, whereby the potentiometer is of high sensitivity, durable in use, low in cost, easily converted from a conventional rheostat and fit for mass production.
摘要翻译：电位计包括轴，底座，其中包括印刷电路板，固定地安装有发光体，以及与发光体相对设置并与发光体隔开的光接收器，所述发光体被供给稳定电压以发光并提供工作电压光接收器，形成有开口并固定安装在轴的上端的圆形座，塑料膜，布置在开口的外边缘并且设置在光发射器和光接收器之间，塑料膜设置两个不透明的端部和从一侧到另一侧的透明度降低的中间部分，以及固定地安装在基座上以封闭圆形座的盖，由此电位计具有高灵敏度，使用寿命低成本，易于从传统的变阻器转换并适合批量生产。

10. 发明授权

US08546885B2 Metal gate electrode of a field effect transistor 有权
标题翻译：场效应晶体管的金属栅电极
公开(公告)号：US08546885B2
公开(公告)日：2013-10-01
申请号：US13189732
申请日：2011-07-25
申请人： Cheng-Hao Hou , Peng-Soon Lim , Da-Yuan Lee , Xiong-Fei Yu , Chun-Yuan Chou , Fan-Yi Hsu , Jian-Hao Chen , Kuang-Yuan Hsu
发明人： Cheng-Hao Hou , Peng-Soon Lim , Da-Yuan Lee , Xiong-Fei Yu , Chun-Yuan Chou , Fan-Yi Hsu , Jian-Hao Chen , Kuang-Yuan Hsu
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.
摘要翻译：公开了集成电路制造，更具体地说，公开了具有低电阻金属栅电极的场效应晶体管。场效应晶体管的金属栅电极的示例性结构包括由第一金属材料形成的下部，其中下部具有凹部，底部和侧壁部分，其中每个侧壁部分具有第一宽度; 以及由第二金属材料形成的上部，其中所述上部具有突起和主体部分，其中所述主体部分具有第二宽度，其中所述突起延伸到所述凹部中，其中所述第二宽度与所述第一宽度的比率宽度为约5至10。

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