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1. 发明授权

US08710485B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08710485B2
公开(公告)日：2014-04-29
申请号：US13458042
申请日：2012-04-27
申请人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
发明人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
IPC分类号： H01L29/06 , H01L47/00
CPC分类号： H01L21/823431 , H01L27/101 , H01L27/1211 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.
摘要翻译：根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。

2. 发明授权

US08932915B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08932915B2
公开(公告)日：2015-01-13
申请号：US13082103
申请日：2011-04-07
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336 , B82Y10/00 , H01L21/84 , H01L27/06 , H01L27/115 , H01L27/12 , H01L29/04 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/792 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

3. 发明授权

US08907406B2 Transistor having impurity distribution controlled substrate and method of manufacturing the same 有权
标题翻译：具有杂质分布受控衬底的晶体管及其制造方法
公开(公告)号：US08907406B2
公开(公告)日：2014-12-09
申请号：US13729959
申请日：2012-12-28
申请人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka , Yusuke Higashi
发明人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka , Yusuke Higashi
IPC分类号： H01L29/66 , H01L29/786 , H01L29/06 , H01L29/32 , B82Y40/00 , H01L29/775 , H01L29/78 , B82Y10/00
CPC分类号： H01L29/32 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78603 , H01L29/78696
摘要： A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
摘要翻译：根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的掩埋绝缘层，形成在掩埋绝缘层上并且包括狭窄部分和比窄部分大的两个宽部分的半导体层并且分别连接到窄部分的一端和另一端，形成在窄部分的侧表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。直接在窄部下方的半导体衬底的杂质浓度高于窄部分的杂质浓度，并且直接在窄部下方的半导体衬底的杂质浓度高于直接在宽度以下的半导体衬底的杂质浓度一部分。

4. 发明申请

US20120282743A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20120282743A1
公开(公告)日：2012-11-08
申请号：US13487295
申请日：2012-06-04
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/266 , H01L21/823437 , H01L21/823462 , H01L21/845 , H01L27/1211 , H01L29/66628 , H01L29/785
摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
摘要翻译：在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

5. 发明申请

US20120235152A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120235152A1
公开(公告)日：2012-09-20
申请号：US13236199
申请日：2011-09-19
申请人： Kensuke OTA , Masumi Saitoh , Toshinori Numata
发明人： Kensuke OTA , Masumi Saitoh , Toshinori Numata
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/26506 , H01L21/26586 , H01L29/42392 , H01L29/66742 , H01L29/66803 , H01L29/785 , H01L29/78696
摘要： A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.
摘要翻译：根据实施例的半导体器件包括：形成在绝缘膜上的多晶半导体层，所述多晶半导体层包括第一区域和第二和第三区域，所述第二区域和第三区域各自具有比所述第一区域更大的宽度，所述第二和第三区域中的一个是连接到第一区域; 形成在所述多晶半导体层的所述第一区域的至少一侧面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及由绝缘材料制成的栅极侧壁，所述栅极侧壁形成在所述第二和第三区域侧面上的所述栅电极的侧面上。第一区域中每单位体积杂质的含量大于第二和第三区域中每单位体积杂质的含量。

6. 发明申请

US20120146053A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146053A1
公开(公告)日：2012-06-14
申请号：US13237697
申请日：2011-09-20
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi , Kensuke Ota
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi , Kensuke Ota
IPC分类号： H01L29/161 , H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7843
摘要： A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.
摘要翻译：根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在栅电极两侧的第一栅极侧壁和源极/漏极半导体层，形成在半导体衬底上，以与栅电极夹住第一栅极侧壁。此外，第二栅极侧壁设置在栅电极两侧的第一栅极侧壁和源极/漏极半导体层上，其中每个第二栅极侧壁与每个第一栅极侧壁的边界在侧表面终止并且每个第二栅极侧壁具有比每个第一栅极侧壁更小的杨氏模量和更低的介电常数。

7. 发明授权

US08999801B2 Nanowire channel field effect device and method for manufacturing the same 有权
标题翻译：纳米线通道场效应装置及其制造方法
公开(公告)号：US08999801B2
公开(公告)日：2015-04-07
申请号：US13236199
申请日：2011-09-19
申请人： Kensuke Ota , Masumi Saitoh , Toshinori Numata
发明人： Kensuke Ota , Masumi Saitoh , Toshinori Numata
IPC分类号： H01L21/336 , H01L29/10 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/265
CPC分类号： H01L29/0673 , H01L21/26506 , H01L21/26586 , H01L29/42392 , H01L29/66742 , H01L29/66803 , H01L29/785 , H01L29/78696
摘要： A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.
摘要翻译：根据实施例的半导体器件包括：形成在绝缘膜上的多晶半导体层，所述多晶半导体层包括第一区域和第二和第三区域，所述第二区域和第三区域各自具有比所述第一区域更大的宽度，所述第二和第三区域中的一个是连接到第一区域; 形成在所述多晶半导体层的所述第一区域的至少一侧面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及由绝缘材料制成的栅极侧壁，所述栅极侧壁形成在所述第二和第三区域侧面上的所述栅电极的侧面上。第一区域中每单位体积杂质的含量大于第二和第三区域中每单位体积杂质的含量。

8. 发明授权

US08518769B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08518769B2
公开(公告)日：2013-08-27
申请号：US13415592
申请日：2012-03-08
申请人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka
发明人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/786 , H01L29/00 , H01L29/785 , H01L29/78696
摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.
摘要翻译：实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

9. 发明授权

US08492219B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08492219B2
公开(公告)日：2013-07-23
申请号：US13487295
申请日：2012-06-04
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L21/8234 , H01L21/337 , H01L21/8232 , H01L21/336 , H01L21/00
CPC分类号： H01L27/0207 , H01L21/266 , H01L21/823437 , H01L21/823462 , H01L21/845 , H01L27/1211 , H01L29/66628 , H01L29/785
摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
摘要翻译：在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

10. 发明申请

US20110303972A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110303972A1
公开(公告)日：2011-12-15
申请号：US13082103
申请日：2011-04-07
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

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