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1. 发明申请

US20070158739A1 Higher performance CMOS on (110) wafers 审中-公开
标题翻译：更高性能CMOS（110）晶圆
公开(公告)号：US20070158739A1
公开(公告)日：2007-07-12
申请号：US11327256
申请日：2006-01-06
申请人： Massimo Fischetti , Qiqing Ouyang
发明人： Massimo Fischetti , Qiqing Ouyang
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/045 , H01L29/7842 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.
摘要翻译：提供了在迁移率增强方面形成在（110）衬底上的具有改进性能的半导体（例如，互补金属氧化物半导体（CMOS））结构。根据本发明，本发明的结构包括与（110）衬底结合使用的单张力应力衬垫，压应力浅沟槽隔离（STI）区域或拉伸应力嵌入井中的至少一个以改善nFET和pFET的载流子迁移率。本发明还涉及一种提供这种结构的方法。

2. 发明授权

US08664721B2 FET with FUSI gate and reduced source/drain contact resistance 有权
标题翻译：具有FUSI栅极的FET和降低的源极/漏极接触电阻
公开(公告)号：US08664721B2
公开(公告)日：2014-03-04
申请号：US13569741
申请日：2012-08-08
申请人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
IPC分类号： H01L27/12 , H01L29/45
CPC分类号： H01L29/66575 , H01L21/265 , H01L21/28097 , H01L29/458 , H01L29/4908 , H01L29/4975 , H01L29/66507 , H01L29/66545 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
摘要翻译：场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

3. 发明授权

US07227205B2 Strained-silicon CMOS device and method 有权
标题翻译：应变硅CMOS器件及方法
公开(公告)号：US07227205B2
公开(公告)日：2007-06-05
申请号：US10930404
申请日：2004-08-31
申请人： Andres Bryant , Qiqing Ouyang , Kern Rim
发明人： Andres Bryant , Qiqing Ouyang , Kern Rim
IPC分类号： H01L29/76
CPC分类号： H01L29/165 , H01L29/1054 , H01L29/24 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

4. 发明申请

US20070001262A1 SOI bipolar transistors with reduced self heating 失效
标题翻译：具有自加热降低的SOI双极晶体管
公开(公告)号：US20070001262A1
公开(公告)日：2007-01-04
申请号：US11173540
申请日：2005-07-01
申请人： Qiqing Ouyang , Kai Xiu
发明人： Qiqing Ouyang , Kai Xiu
IPC分类号： H01L27/082
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203
摘要： A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.
摘要翻译：双极晶体管包括位于衬底上方的集电极; 以及将基板连接到集电体的导热路径。导热路径填充有诸如金属或多晶硅的导热材料。在一个实施例中，导热路径穿过收集器以从集电器提取热量并将其排出到基板。在替代实施例中，晶体管可以是垂直或横向装置。根据另一实施例，使用BiCMOS技术的集成电路包括具有从集电极到衬底以及可能的p沟道和n沟道MOSFET的热传导的pnp和npn双极晶体管。根据另一个实施例，一种用于在集成网络中制造晶体管的方法包括以下步骤：蚀刻通过集电器和衬底的导热路径，并填充导热材料，以为包括集电器的晶体管提供散热。

5. 发明申请

US20050184360A1 Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof 有权
标题翻译：具有用于低衬底偏置操作的薄埋氧化物（BOX）上的反向集电极的超薄SOI垂直双极晶体管及其方法
公开(公告)号：US20050184360A1
公开(公告)日：2005-08-25
申请号：US10787002
申请日：2004-02-25
申请人： Herbert Ho , Mahender Kumar , Qiqing Ouyang , Paul Papworth , Christopher Sheraw , Michael Steigerwalt
发明人： Herbert Ho , Mahender Kumar , Qiqing Ouyang , Paul Papworth , Christopher Sheraw , Michael Steigerwalt
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/082 , H01L27/12 , H01L29/73 , H01L29/732
CPC分类号： H01L29/7317
摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
摘要翻译：本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

6. 发明申请

US20050077510A1 Structure for and method of fabricating a high-mobility field-effect transistor 有权
标题翻译：制造高迁移率场效应晶体管的结构和方法
公开(公告)号：US20050077510A1
公开(公告)日：2005-04-14
申请号：US10685013
申请日：2003-10-14
申请人： Jack Chu , Steven Koester , Qiqing Ouyang
发明人： Jack Chu , Steven Koester , Qiqing Ouyang
IPC分类号： H01L29/06 , H01L21/20 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812 , H01L31/0328 , H01L21/336
CPC分类号： H01L29/66431 , H01L29/7782 , Y10S438/933 , Y10S438/938
摘要： A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.
摘要翻译：制造高迁移率半导体层结构的结构和方法以及包括高迁移率导电沟道的场效应晶体管（MODFET），同时保持反掺杂以控制有害的短沟道效应。 MODFET设计包括高迁移率导电沟道层，其中该方法允许使用诸如离子注入的标准技术形成反相掺杂，并且还允许高迁移率通道紧邻反掺杂而不降解流动性。

7. 发明授权

US06812533B2 SOI based bipolar transistor having a majority carrier accumulation layer as subcollector 有权
标题翻译：具有多数载流子积累层的SOI基双极晶体管作为子集电极
公开(公告)号：US06812533B2
公开(公告)日：2004-11-02
申请号：US10328694
申请日：2002-12-24
申请人： Jin Cai , Tak H. Ning , Qiqing Ouyang
发明人： Jin Cai , Tak H. Ning , Qiqing Ouyang
IPC分类号： H01L2976
CPC分类号： H01L29/66265 , H01L29/0821 , H01L29/7317
摘要： An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.
摘要翻译：电子电路包括双极晶体管，其包括导电背电极，导电背电极之上的绝缘体层以及绝缘体层上的n型或p型材料的半导体层。半导体层包括用作集电极的掺杂区域和与掺杂区域接壤的重掺杂区域，用作绝缘体层和集电极接触电极之间的穿透层。通过向背电极施加偏置电压，在集电极的掺杂区域中与绝缘体相邻地吸引多数载流子堆积层。

8. 发明授权

US06319799B1 High mobility heterojunction transistor and method 失效
标题翻译：高迁移率异质结晶体管及方法
公开(公告)号：US06319799B1
公开(公告)日：2001-11-20
申请号：US09568091
申请日：2000-05-09
申请人： Qiqing Ouyang , Al F. Tasch, Jr. , Sanjay Kumar Banerjee
发明人： Qiqing Ouyang , Al F. Tasch, Jr. , Sanjay Kumar Banerjee
IPC分类号： H01L21425
CPC分类号： H01L29/1054 , H01L29/7782
摘要： A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.
摘要翻译：在沟道区域中具有高迁移率载流子的异质结晶体管包括形成在半导体本体中的源极区和漏极区，源极区和漏极区包括通过异质结从衬底分离的掺杂半导体合金。在源极区域和漏极区域之间设置有沟道区域，该区域包括半导体材料的合金的未掺杂层和覆盖未掺杂层的半导体器件的沉积层。在沟道区上的栅极氧化物上形成栅电极。在制造高迁移率异质结晶体管时，通过注入与衬底相反的导电类型的掺杂剂和合金中的材料，在衬底中形成间隔的源极和漏极区域，然后对该结构进行退火，以形成半导体材料的合金未掺杂层

9. 发明授权

US07968915B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07968915B2
公开(公告)日：2011-06-28
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

10. 发明申请

US20080303101A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20080303101A1
公开(公告)日：2008-12-11
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed,
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中，

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