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1. 发明申请

US20050237042A1 Switching power supply circuit and semiconductor device integrating the same 审中-公开
标题翻译：开关电源电路和集成其的半导体器件
公开(公告)号：US20050237042A1
公开(公告)日：2005-10-27
申请号：US11106085
申请日：2005-04-14
申请人： Masato Yoshida , Takashi Ryu , Kazuyuki Moritake
发明人： Masato Yoshida , Takashi Ryu , Kazuyuki Moritake
IPC分类号： G05F1/40 , H02M3/145 , H02M3/156 , H02M3/335
CPC分类号： H02M3/156
摘要： A switching power supply circuit in accordance with the present invention is configured such that a switched-capacitor circuit is provided between an output terminal for outputting an output voltage and an input of an error amplification circuit, the output signal from the error amplification circuit for amplifying the error between a DC output voltage and a reference voltage is compared with a reference signal by a pulse width modulation circuit, and a voltage conversion section is turned ON/OFF continuously using the output signal of a pulse width modulation circuit while having a predetermined period with respect to an input voltage.
摘要翻译：根据本发明的开关电源电路被配置为使得开关电容器电路设置在用于输出输出电压的输出端和误差放大电路的输入之间，来自用于放大的误差放大电路的输出信号通过脉冲宽度调制电路将直流输出电压与参考电压之间的误差与参考信号进行比较，并且使用脉冲宽度调制电路的输出信号连续地使电压转换部分接通/断开，同时具有预定周期相对于输入电压。

2. 发明申请

US20070085566A1 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20070085566A1
公开(公告)日：2007-04-19
申请号：US11495774
申请日：2006-07-31
申请人： Masaaki Koto , Kazuhito Kimura , Takuya Ishii , Kazuyuki Moritake
发明人： Masaaki Koto , Kazuhito Kimura , Takuya Ishii , Kazuyuki Moritake
IPC分类号： H03K19/0175
CPC分类号： H03K3/356104
摘要： A level shift circuit has a driving circuit and an output circuit. The driving circuit has a clamp circuit for receiving first and second bias potentials, outputting first and second drive signals which are not less than a reference potential, less than the first bias potential, and complementary to each other, and also outputting third and fourth drive signals which are higher than the second bias potential, not more than a power source potential, and complementary to each other. The output circuit has a first output transistor of a first conductivity type and a second output transistor of a second conductivity type which are connected in series to each other. The first output transistor has a gate for receiving the first drive signal and one electrode for receiving the reference potential. The second output transistor has a gate for receiving the third drive signal and one electrode for receiving the power source potential.
摘要翻译：电平移位电路具有驱动电路和输出电路。驱动电路具有用于接收第一和第二偏置电位的钳位电路，输出小于第一偏置电位并且彼此互补的不小于参考电位的第一和第二驱动信号，并且还输出第三和第四驱动高于第二偏置电位的信号，不大于电源电位，彼此互补。输出电路具有彼此串联连接的第一导电类型的第一输出晶体管和第二导电类型的第二输出晶体管。第一输出晶体管具有用于接收第一驱动信号的栅极和用于接收参考电位的一个电极。第二输出晶体管具有用于接收第三驱动信号的栅极和用于接收电源电位的一个电极。

3. 发明申请

US20080252354A1 OUTPUT CIRCUIT 有权
标题翻译：输出电路
公开(公告)号：US20080252354A1
公开(公告)日：2008-10-16
申请号：US12059789
申请日：2008-03-31
申请人： Masaaki Koto , Kazuhito Kimura , Kazuyuki Moritake , Takuya Ishii
发明人： Masaaki Koto , Kazuhito Kimura , Kazuyuki Moritake , Takuya Ishii
IPC分类号： H03K5/08 , H03L5/00
CPC分类号： H03K19/018521
摘要： An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.
摘要翻译：输出电路包括输出块和用于基于输入信号驱动输出块的预驱动块。预驱动块具有连接在第一输出晶体管的栅极端子和第二输出晶体管的栅极端子之间的钳位单元，以将第一输出晶体管的栅极端子的电位限制在不大于第一电位的值;以及将第二输出晶体管的栅极端子的电位限制在不小于第二电位的值。

4. 发明授权

US07348800B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US07348800B2
公开(公告)日：2008-03-25
申请号：US11495774
申请日：2006-07-31
申请人： Masaaki Koto , Kazuhito Kimura , Takuya Ishii , Kazuyuki Moritake
发明人： Masaaki Koto , Kazuhito Kimura , Takuya Ishii , Kazuyuki Moritake
IPC分类号： H03K19/0175
CPC分类号： H03K3/356104
摘要： A level shift circuit has a driving circuit and an output circuit. The driving circuit has a clamp circuit for receiving first and second bias potentials, outputting first and second drive signals which are not less than a reference potential, less than the first bias potential, and complementary to each other, and also outputting third and fourth drive signals which are higher than the second bias potential, not more than a power source potential, and complementary to each other. The output circuit has a first output transistor of a first conductivity type and a second output transistor of a second conductivity type which are connected in series to each other. The first output transistor has a gate for receiving the first drive signal and one electrode for receiving the reference potential. The second output transistor has a gate for receiving the third drive signal and one electrode for receiving the power source potential.
摘要翻译：电平移位电路具有驱动电路和输出电路。驱动电路具有用于接收第一和第二偏置电位的钳位电路，输出小于第一偏置电位并且彼此互补的不小于参考电位的第一和第二驱动信号，并且还输出第三和第四驱动高于第二偏置电位的信号，不大于电源电位，彼此互补。输出电路具有彼此串联连接的第一导电类型的第一输出晶体管和第二导电类型的第二输出晶体管。第一输出晶体管具有用于接收第一驱动信号的栅极和用于接收参考电位的一个电极。第二输出晶体管具有用于接收第三驱动信号的栅极和用于接收电源电位的一个电极。

5. 发明授权

US07737735B2 Output circuit for outputting a signal with a high-voltage amplitude 有权
标题翻译：用于输出具有高电压幅度的信号的输出电路
公开(公告)号：US07737735B2
公开(公告)日：2010-06-15
申请号：US12059789
申请日：2008-03-31
申请人： Masaaki Koto , Kazuhito Kimura , Kazuyuki Moritake , Takuya Ishii
发明人： Masaaki Koto , Kazuhito Kimura , Kazuyuki Moritake , Takuya Ishii
IPC分类号： H03K3/00
CPC分类号： H03K19/018521
摘要： An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.
摘要翻译：输出电路包括输出块和用于基于输入信号驱动输出块的预驱动块。预驱动块具有连接在第一输出晶体管的栅极端子和第二输出晶体管的栅极端子之间的钳位单元，以将第一输出晶体管的栅极端子的电位限制在不大于第一电位的值;以及将第二输出晶体管的栅极端子的电位限制在不小于第二电位的值。

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