专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06392413B1 Short circuit inspection method for battery and method of manufacturing batteries 有权
公开(公告)号：US06392413B1
公开(公告)日：2002-05-21
申请号：US09788536
申请日：2001-02-21
申请人： Masato Onishi , Hideo Asaka , Katsuyuki Tomioka , Noriyuki Fujioka
发明人： Masato Onishi , Hideo Asaka , Katsuyuki Tomioka , Noriyuki Fujioka
IPC分类号： G01N27416
摘要： In a method of inspecting batteries for short circuit failures, an electrode plate group 1 composed of positive and negative electrode plates 2, 3 with intervening separators 4 interposed therebetween is set on a pressing station 7, where it is compressed during short-circuiting inspection is performed, for simulating a state wherein separators are compressed by swelling electrode plates 2, 3 during charging and discharging of battery.

2. 发明授权

US06544684B2 Prismatic battery and method of manufacturing same 有权
标题翻译：棱镜电池及其制造方法
公开(公告)号：US06544684B2
公开(公告)日：2003-04-08
申请号：US09825987
申请日：2001-04-05
申请人： Masato Onishi , Hideo Asaka , Hiroshi Nagata , Noriyuki Fujioka , Shinji Hamada
发明人： Masato Onishi , Hideo Asaka , Hiroshi Nagata , Noriyuki Fujioka , Shinji Hamada
IPC分类号： H01M1040
CPC分类号： H01M10/0413 , H01M2/266 , Y10T29/49108
摘要： Positive and negative electrode plates 2, 3 are alternately stacked upon one another with intervening separators 4 to constitute an electrode plate group 1. The respective electrode plates are laterally offset so that side edges of the electrode plates protrude on the opposite sides. Collector plates 5, 6 are perpendicularly welded to the side edges of the electrode plates 2, 3 on both sides of the electrode plate group 1. Loose ends 3c, 3e of the outermost negative electrode plates 3b, 3d that are not welded to the collector plate are secured to the electrode plate group by a holding tape 7.
摘要翻译：正极板和负极板2,3彼此交替地堆叠有中间隔板4以构成电极板组1.各个电极板横向偏移，使得电极板的侧边缘在相对的两侧突出。在电极板组1的两侧将集电板5,6垂直焊接到电极板2,3的侧边缘。最外侧的负极板3b，3d的没有焊接到集电体的端部3c，3e 板通过保持带7固定到电极板组。

3. 发明授权

US5689469A Semiconductor memory devices 失效
标题翻译：半导体存储器件
公开(公告)号：US5689469A
公开(公告)日：1997-11-18
申请号：US742537
申请日：1996-11-01
申请人： Hideo Asaka , Hiroyuki Yamauchi
发明人： Hideo Asaka , Hiroyuki Yamauchi
IPC分类号： G11C8/08 , G11C11/408 , G11C11/4094 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/4085 , G11C29/02 , G11C29/50 , G11C8/08 , G11C11/401
摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.
摘要翻译：当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。在将上述公共电源线连接到地线的路径中设置有阻抗改变装置，用于改变在待机期间的值之间的路径的阻抗和在其中选择任何字线的操作期间的另一个值，使得待机期间的值为设置高于操作期间的值。因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

4. 发明授权

US5594701A Semiconductor memory device having a plurality of blocks 失效
标题翻译：具有多个块的半导体存储器件
公开(公告)号：US5594701A
公开(公告)日：1997-01-14
申请号：US420875
申请日：1995-04-13
申请人： Hideo Asaka , Hiroyuki Yamauchi
发明人： Hideo Asaka , Hiroyuki Yamauchi
IPC分类号： G11C8/08 , G11C11/408 , G11C11/4094 , G11C29/02 , G11C29/50 , G11C8/00 , G11C29/00
CPC分类号： G11C11/4094 , G11C11/4085 , G11C29/02 , G11C29/50 , G11C8/08 , G11C11/401
摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another valve during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.
摘要翻译：当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。在将上述公共电源线连接到地面的路径中设置有阻抗改变装置，用于改变在待机期间的值与操作期间的另一个阀之间的路径的阻抗，在此期间选择任何字线，使得待机期间的值为设置高于操作期间的值。因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

5. 发明授权

US5748520A Semiconductor memory device having minimal leakage current 失效
标题翻译：具有最小漏电流的半导体存储器件
公开(公告)号：US5748520A
公开(公告)日：1998-05-05
申请号：US741618
申请日：1996-10-31
申请人： Hideo Asaka , Hiroyuki Yamauchi
发明人： Hideo Asaka , Hiroyuki Yamauchi
IPC分类号： G11C8/08 , G11C11/408 , G11C11/4094 , G11C29/02 , G11C29/50 , G11C11/24
CPC分类号： G11C11/4094 , G11C11/4085 , G11C29/02 , G11C29/50 , G11C8/08 , G11C11/401
摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.
摘要翻译：当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。在将上述公共电源线连接到地线的路径中设置有阻抗改变装置，用于改变在待机期间的路径之间的路径阻抗和操作期间的另一个值，在此期间选择任何字线，使得待机期间的值为设置高于操作期间的值。因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式