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1. 发明申请

US20050098835A1 Semiconductor device and semiconductor integrated circuit device 有权
标题翻译：半导体器件和半导体集成电路器件
公开(公告)号：US20050098835A1
公开(公告)日：2005-05-12
申请号：US10975956
申请日：2004-10-29
申请人： Masaru Ushiroda , Hiroshi Furuta
发明人： Masaru Ushiroda , Hiroshi Furuta
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L21/8239 , H01L21/8244 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11 , H01L29/76
CPC分类号： H01L27/11 , H01L27/0921 , H01L27/105 , H01L27/1052
摘要： Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. Pwells andN wells are formedin a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer underlying thereof. A PMOSFET is formed in the N well and a NMOSFET is formed in the P well. A P well electric potential junction for coupling P well electric potential of the P well to predetermined electric potential is provided, and a region directly under the P well electric potential junction is provided with a region where the aforementioned buried N well is not disposed. The soft-error resistance is improved by having the buried N well therein, and the latch up resistance is improved by coupling the P well to the substrate.
摘要翻译：涉及小型化和降低工作电压的LSI同时提高了软误差电阻和闭锁电阻。在较高密度的衬底（P +衬底上的P）上形成孔和N阱，并且在其下面的层上形成掩埋的N个阱。在N阱中形成PMOSFET，在P阱中形成NMOSFET。提供用于将P阱的P阱电位耦合到预定电位的P阱电位结，并且在P阱电位结下方的区域设置有未设置上述埋入N阱的区域。通过在其中埋入N阱来提高软误差电阻，并且通过将P阱耦合到衬底来提高闭锁电阻。

2. 发明授权

US07214989B2 Semiconductor device and semiconductor integrated circuit device 有权
标题翻译：半导体器件和半导体集成电路器件
公开(公告)号：US07214989B2
公开(公告)日：2007-05-08
申请号：US10975956
申请日：2004-10-29
申请人： Masaru Ushiroda , Hiroshi Furuta
发明人： Masaru Ushiroda , Hiroshi Furuta
IPC分类号： H01L29/94
CPC分类号： H01L27/11 , H01L27/0921 , H01L27/105 , H01L27/1052
摘要： Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. P wells and N wells are formed in a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer underlying thereof. A PMOSFET is formed in the N well and a NMOSFET is formed in the P well. A P well electric potential junction for coupling P well electric potential of the P well to predetermined electric potential is provided, and a region directly under the P well electric potential junction is provided with a region where the aforementioned buried N well is not disposed. The soft-error resistance is improved by having the buried N well therein, and the latch up resistance is improved by coupling the P well to the substrate.
摘要翻译：涉及小型化和降低工作电压的LSI同时提高了软误差电阻和闭锁电阻。 P阱和N阱形成在较高密度的衬底（P +衬底上的P）上，并且在其下面的层上形成掩埋的N个阱。在N阱中形成PMOSFET，在P阱中形成NMOSFET。提供用于将P阱的P阱电位耦合到预定电位的P阱电位结，并且在P阱电位结下方的区域设置有未设置上述埋入N阱的区域。通过在其中埋入N阱来提高软误差电阻，并且通过将P阱耦合到衬底来提高闭锁电阻。

3. 发明授权

US06303422B1 Semiconductor memory and manufacturing method thereof 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US06303422B1
公开(公告)日：2001-10-16
申请号：US09329647
申请日：1999-06-09
申请人： Tomohisa Abe , Masaru Ushiroda , Toshio Komuro
发明人： Tomohisa Abe , Masaru Ushiroda , Toshio Komuro
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L23/522 , H01L23/5226 , H01L23/5228 , H01L23/5286 , H01L23/53223 , H01L27/1112 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.
摘要翻译：提供了一种半导体存储器，其中SRAM的布线层之间的接触孔处的布局边缘不需要，并且位线处的布线容量减小，并且提供了高速处理。 SRAM由一对驱动晶体管Qd1和Qd2，一对转移晶体管Qt1和Qt2，高电阻负载R1和R2，一对位线BL1和BL2以及VCC线和GND线构成。每个晶体管的栅电极和字线形成在第一层，高电阻负载形成在第二层，VCC线和GND线形成在第三层，并且位线形成在第四层。用于将高电阻负载连接到晶体管的源极/漏极区域的共用接触孔不会穿透其它导电层。因此，共用接触孔和其它导电层之间的布局裕度变得不必要，并且可以减小电池尺寸。

4. 发明授权

US06281065B1 Semiconductor device fabrication method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06281065B1
公开(公告)日：2001-08-28
申请号：US09460857
申请日：1999-12-14
申请人： Masaru Ushiroda
发明人： Masaru Ushiroda
IPC分类号： H01L218249
CPC分类号： H01L21/76221 , H01L21/8249
摘要： In order to define region in which a bipolar transistor is formed, region in which a MOS transistor is formed, and another predetermined region upon a substrate of p-type silicon, the substrate is selectively oxidized (by the LOCOS method). An element isolation region 200-500 nm thick is thereby formed. Then, a silicon oxide film 550 nm thick on the substrate, a silicon nitride film (an oxidation-resistant film) 100-300 nm thick, and a silicon oxide film 5-50 nm thick are formed. Thereafter, a publicly known photolithographic technique is used to form a photoresist pattern having an opening, and then, using the pattern as a mask, the silicon oxide film on the opening is removed. The bipolar transistor and the MOS transistor are thereby integrated in a monolithic manner without degrading the characteristics of the respective elements.
摘要翻译：为了限定形成双极晶体管的区域，其中形成MOS晶体管的区域和p型硅衬底上的另一个预定区域，衬底被选择性氧化（通过LOCOS方法）。由此形成200-500nm厚的元件隔离区。然后，在衬底上形成550nm厚的氧化硅膜，100-300nm厚的氮化硅膜（耐氧化膜）和5-50nm厚的氧化硅膜。此后，使用公知的光刻技术来形成具有开口的光致抗蚀剂图案，然后使用图案作为掩模，去除开口上的氧化硅膜。因此，双极晶体管和MOS晶体管以单片方式集成，而不会降低各元件的特性。

5. 发明授权

US07646052B2 DRAM and SRAM mixedly mounted semiconductor device 失效
标题翻译： DRAM和SRAM混合安装的半导体器件
公开(公告)号：US07646052B2
公开(公告)日：2010-01-12
申请号：US11867198
申请日：2007-10-04
申请人： Takami Nagata , Masaru Ushiroda
发明人： Takami Nagata , Masaru Ushiroda
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/10897 , H01L27/11 , H01L27/1116 , Y10S257/903
摘要： A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.
摘要翻译：提供其中混合安装DRAM和SRAM的半导体器件。 DRAM和SRAM具有堆叠型结构，其中位线形成在电容元件下方。 SRAM的交叉耦合连接形成在其中形成DRAM的电容性下电极的层中或层的下方，或者形成在其中形成位线的层中或上方的层中。例如，SRAM的交叉耦合连接形成在与电容性接触相同的层中。

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