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    • 5. 发明授权
    • Class D amplifier
    • D类放大器
    • US06937091B2
    • 2005-08-30
    • US10632248
    • 2003-08-01
    • Yasuomi TanakaMasao Noro
    • Yasuomi TanakaMasao Noro
    • H03K17/687H03F3/217H03F3/30H03F3/38
    • H03F3/2171
    • A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305) complementarily drive power-MOS transistors (401, 402).
    • 互补信号发生电路(301)从PWM信号产生第一互补信号(S1,S2)。 信号转换电路(302)将第一互补信号转换成具有基于负电源(VPP-)的电压分量的第二互补信号(S 3,S 4或S 5,S 6)。 在第二互补信号中,信号(S 3,S 4)被提供给驱动电路(305),并且信号(S 5,S 6)被提供给电流驱动电路(303)。 响应于信号(S 5,S 6),电流驱动电路将具有指向负电源(VPP-)的电流分量的第三互补信号(H 3,H 4)输出到驱动电路 304)。 结果,驱动电路(304,305)互补驱动功率MOS晶体管(401,402)。
    • 6. 发明授权
    • Operational amplifier
    • 运算放大器
    • US06903607B2
    • 2005-06-07
    • US10623826
    • 2003-07-21
    • Nobuaki TsujiMasao NoroKunihiko Mitsuoka
    • Nobuaki TsujiMasao NoroKunihiko Mitsuoka
    • H03F3/45
    • H03F3/45188
    • An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.
    • 运算放大器具有差分放大级,该差分放大级包括一对第一PMOS晶体管,用于输入信号,该第一PMOS晶体管布置在与第一恒流源耦合的正电压源和负电压源之间,其中高耐压型的第二PMOS晶体管 其栅极被偏置到规定的电压,被布置在与负载电阻器一起位于第一PMOS晶体管和负电压源之间的电流路径上。 这里,第一PMOS晶体管的漏极电压的每一个被限制为比栅极阈值电压高于规定电压的一定值。 因此,即使当第一PMOS晶体管由正常耐压型构成时,也可以可靠地防止施加到第一PMOS晶体管的电压超过其击穿电压,从而避免不必要地降低S / N比。
    • 7. 发明授权
    • Self-operating PWM amplifier
    • 自动PWM放大器
    • US06707337B2
    • 2004-03-16
    • US10253077
    • 2002-09-24
    • Masao Noro
    • Masao Noro
    • H03F338
    • H03F3/2173
    • Differential integrator circuit integrates a differential between a difference between a signal supplied from a first signal source and a feedback signal of amplifier output and a difference between a signal supplied from a second signal source and a feedback signal of the amplifier output. The signal supplied from the second signal source is opposite in phase from the signal supplied from the first signal source. Thus, the integrator circuit outputs two integrated signals of different polarities. Comparator compares the two integrated signals from the integrator circuit to thereby output a PWM signal. First driver circuit amplifies the PWM signal and outputs the amplified PWM signal with inverted phase, and a second driver circuit amplifies the PWM signal and outputs the amplified PWM signal with noninverted phase. First switching circuit is driven by the output of the first driver circuit, while a second switching circuit is driven by the output of the second driver circuit.
    • 差分积分器电路将从第一信号源提供的信号与放大器输出的反馈信号之间的差与由第二信号源提供的信号与放大器输出的反馈信号之间的差进行积分。 从第二信号源提供的信号与从第一信号源提供的信号的相位相反。 因此,积分器电路输出具有不同极性的两个积分信号。 比较器比较来自积分器电路的两个积分信号,从而输出PWM信号。 第一驱动电路放大PWM信号并输出​​反相放大的PWM信号,第二驱动电路放大PWM信号并以非反相输出放大的PWM信号。 第一开关电路由第一驱动电路的输出驱动,而第二开关电路由第二驱动电路的输出驱动。
    • 8. 发明授权
    • Analog-to-digital converter
    • 模数转换器
    • US06703958B2
    • 2004-03-09
    • US09870153
    • 2001-05-30
    • Masao Noro
    • Masao Noro
    • H03M112
    • H03M1/48
    • A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.
    • 将从外部模拟信号源顺序产生的外部模拟信号转换成n位数字数据信号(n为2以上的整数)的高效率模数(A / D)转换电路包括: 一个将n位数字数据信号转换为模拟信号并从第一输出端输出模拟信号的数/模(D / A)转换器电路,比较器,用于比较提供的外部模拟信号的信号电平 从具有从第一输出端子输出的模拟信号的信号电平的外部装置,以及数字积分电路,对从比较器输出的1位数字数据信号进行数字积分,从而产生n位数字数据信号。
    • 9. 发明授权
    • Class D amplifier
    • D类放大器
    • US06696891B2
    • 2004-02-24
    • US10251169
    • 2002-09-20
    • Masao NoroYasuhiko Sekimoto
    • Masao NoroYasuhiko Sekimoto
    • H03F338
    • H03F3/2171H03F2200/331
    • A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.
    • D类放大器包括:积分电路(1),其对输入信号进行积分; 闪存A / D转换器(2),其对所述积分电路的输出信号进行A / D转换; 波形转换电路(3),其基于闪存A / D转换器的输出产生PWM信号; 开关电路,包括连接在第一电源和第二电源之间的一对MOS晶体管(5,6),所述一对MOS晶体管的接点P连接到扬声器(51); 驱动电路(4),其基于所述PWM信号驱动所述一对MOS晶体管; 以及连接在积分电路的接合点P和输入侧之间的反馈电阻器(RNF),并且负反馈放大器的输出信号。
    • 10. 发明授权
    • A/D conversion apparatus
    • A / D转换装置
    • US06445320B1
    • 2002-09-03
    • US09492442
    • 2000-01-27
    • Masao NoroAkira SogoRyo Kamiya
    • Masao NoroAkira SogoRyo Kamiya
    • H03M162
    • H03M3/49
    • An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range. To effectively reduce noise of the output digital signal while securing a wide dynamic range of A/D conversion, the &Dgr;&Sgr; modulator may also control the gain of the input signal based on the control signal to a predetermined value (1/A) smaller than 1, and the decimation circuit may have a gain of a second predetermined value (A) for compensating for the gain of the input signal controlled to the predetermined value (1/A).
    • 提供了一种A / D转换装置,其能够通过在预定电平之间适当地切换输入模拟信号的输入增益,以简单的结构确保宽动态范围的A / D转换。 输入增益控制装置基于控制信号来控制输入信号的增益。 DELTASIGMA调制器对输入信号进行过采样,该输入信号的增益由输入增益控制装置控制,以将输入信号转换成一位的数据。 检测装置根据一位的数据来检测输入信号的峰值。 增益控制装置基于由检测装置检测的峰值以使得其控制增益的输入信号落在预定范围内的方式产生控制信号。 为了有效地降低输出数字信号的噪声,同时确保宽的动态范围的A / D转换,DELTASIGMA调制器还可以基于控制信号将输入信号的增益控制到小于1的预定值(1 / A) ,并且抽取电路可以具有用于补偿被控制到预定值(1 / A)的输入信号的增益的第二预定值(A)的增益。