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1. 发明授权

US07562184B2 DRAM controller for graphics processing operable to enable/disable burst transfer 有权
标题翻译：用于图形处理的DRAM控制器可操作以启用/禁用突发传送
公开(公告)号：US07562184B2
公开(公告)日：2009-07-14
申请号：US11023570
申请日：2004-12-29
申请人： Masanori Henmi , Kazushi Kurata
发明人： Masanori Henmi , Kazushi Kurata
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28 , G09G5/39 , G06F13/372 , G06F12/02 , G09G5/36
CPC分类号： G09G5/393 , G09G5/363 , G09G2360/128 , G11C7/1042
摘要： An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.
摘要翻译：接口单元20将不同的SDRAM 1和2分配给帧缓冲区中的相邻绘图块。在跨越相邻绘图块的处理中，例如，有效命令被交替地发送到SDRAM 1和2，以减少由发布间隔限制引起的等待周期。此外，由于各个时钟使能信号CKE1和CKE2被输出到SDRAM 1和2，使得可以单独停止SDRAM 1和2的突发传送，所以不需要循环来停止突发传输。

2. 发明申请

US20050152211A1 DRAM controller and DRAM control method 有权
标题翻译： DRAM控制器和DRAM控制方式
公开(公告)号：US20050152211A1
公开(公告)日：2005-07-14
申请号：US11023570
申请日：2004-12-29
申请人： Masanori Henmi , Kazushi Kurata
发明人： Masanori Henmi , Kazushi Kurata
IPC分类号： G06F12/02 , G06F12/06 , G06F13/16 , G06T1/00 , G09G5/36 , G09G5/393 , G11C7/10 , G11C8/00
CPC分类号： G09G5/393 , G09G5/363 , G09G2360/128 , G11C7/1042
摘要： An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.
摘要翻译：接口单元20将不同的SDRAM 1和2分配给帧缓冲区中的相邻绘图块。在跨越相邻绘图块的处理中，例如，有效命令被交替地发送到SDRAM 1和2，以减少由发布间隔限制引起的等待周期。此外，由于各个时钟使能信号CKE 1和CKE 2被输出到SDRAM 1和2，所以能够单独停止SDRAM 1和2的突发传输，所以不需要周期来停止突发传输。

3. 发明授权

US06927776B2 Data transfer device and method 失效
标题翻译：数据传输装置及方法
公开(公告)号：US06927776B2
公开(公告)日：2005-08-09
申请号：US10146892
申请日：2002-05-17
申请人： Yoshiteru Mino , Masanori Henmi , Kenji Matsushita
发明人： Yoshiteru Mino , Masanori Henmi , Kenji Matsushita
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405
摘要： The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.
摘要翻译：用于在系统总线和具有帧缓冲区域和一般区域的本地存储器之间传送数据的数据传送装置包括接口部分和数据处理器。基于用于控制从系统总线发送的数据传送的控制数据，接口部分生成用于访问帧缓冲区域和一般区域中的一个的传送参数，并且输出生成的传送参数，以及向系统总线传送数据。数据处理器根据传送参数产生要在本地存储器中传送的数据的地址，并且除了从接口部分传送数据之外还使用生成的地址将数据传送到本地存储器。

4. 发明授权

US08190924B2 Computer system, processor device, and method for controlling computer system 有权
标题翻译：计算机系统，处理器设备和控制计算机系统的方法
公开(公告)号：US08190924B2
公开(公告)日：2012-05-29
申请号：US12146916
申请日：2008-06-26
申请人： Masanori Henmi
发明人： Masanori Henmi
IPC分类号： G06F1/00 , G06F5/00 , G06F3/12 , G06F13/00 , H04M1/00
CPC分类号： G06F13/24 , G06F1/3203
摘要： A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated.
摘要翻译：显着改善对睡眠请求的响应性的计算机系统包括：在执行模式和暂停模式之间切换的处理器设备; 以及访问控制单元，响应于从所述处理器设备接收到的命令请求来访问功能块，其中响应于从所述外部设备接收到的睡眠请求信号，所述处理器设备响应于休眠响应信号并且断言暂停通知指示切换到暂停模式的信号，并且所述访问控制单元在从所述处理器设备接收到所述命令请求之后，在所述访问控制单元输出所述命令请求的情况下，屏蔽所述另外的命令请求的输入接收暂停通知信号; 在处理器设备尚未输出命令请求的情况下掩蔽命令请求的输入; 并且当暂停通知信号被否定时去除该掩码。

5. 发明授权

US08001549B2 Multithreaded computer system and multithread execution control method 有权
标题翻译：多线程计算机系统和多线程执行控制方法
公开(公告)号：US08001549B2
公开(公告)日：2011-08-16
申请号：US11740501
申请日：2007-04-26
申请人： Masanori Henmi
发明人： Masanori Henmi
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/4843 , Y02D10/24
摘要： A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) and a parallel processor controller which switches threads in each PE. The parallel processor controller includes a plurality of execution order registers which hold, for each processor element, an execution order of threads to be executed; a plurality of counters which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler which switches the thread that is being executed to the thread to be executed by each processor element based on an execution order held in the execution order register and the timeout signal.
摘要翻译：本发明的多线程计算机系统包括多个处理器元件（PE）和在每个PE中切换线程的并行处理器控制器。并行处理器控制器包括多个执行顺序寄存器，其对于每个处理器元件保持要执行的线程的执行顺序; 多个计数器，其计数正在由每个处理器单元执行的线程的执行时间，并且当所计数的时间达到分配给所述线程的极限时产生超时信号; 以及线程执行调度器，其基于执行顺序寄存器中保存的执行顺序和超时信号，将正在执行的线程切换到由每个处理器元件执行的线程。

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