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1. 发明申请

US20080278717A1 CONTAMINATION-INSPECTING APPARATUS AND DETECTION CIRCUIT 有权
标题翻译：污染检查装置和检测电路
公开(公告)号：US20080278717A1
公开(公告)日：2008-11-13
申请号：US12116241
申请日：2008-05-07
申请人： Masami Makuuchi , Ritsurou Orihashi , Masayoshi Takahashi , Wen Li , Kengo Imagawa , Takahiro Jingu
发明人： Masami Makuuchi , Ritsurou Orihashi , Masayoshi Takahashi , Wen Li , Kengo Imagawa , Takahiro Jingu
IPC分类号： G01N21/88
CPC分类号： G01N21/9501 , G01N21/94 , G01N2201/1241
摘要： The detection part has: a subtraction module for calculating correction data from data of detection systems when a reference-voltage generation module applies a reference voltage to the detection systems; a data-holding module for holding the correction data; an addition module for making a correction of detection data; a comparison module for comparing the detection data with switching data; and a selector for switching data of the detection systems including data subjected to the correction according to the output of the comparison module.
摘要翻译：检测部具有：减法模块，用于当参考电压产生模块向检测系统施加参考电压时，从检测系统的数据计算校正数据; 用于保持校正数据的数据保持模块; 用于对检测数据进行校正的加法模块; 比较模块，用于将检测数据与切换数据进行比较; 以及选择器，用于根据比较模块的输出来切换包括经过校正的数据的检测系统的数据。

2. 发明授权

US08035071B2 Contamination-inspecting apparatus and detection circuit 有权
标题翻译：污染检查装置和检测电路
公开(公告)号：US08035071B2
公开(公告)日：2011-10-11
申请号：US12116241
申请日：2008-05-07
申请人： Masami Makuuchi , Ritsurou Orihashi , Masayoshi Takahashi , Wen Li , Kengo Imagawa , Takahiro Jingu
发明人： Masami Makuuchi , Ritsurou Orihashi , Masayoshi Takahashi , Wen Li , Kengo Imagawa , Takahiro Jingu
IPC分类号： G01N21/88
CPC分类号： G01N21/9501 , G01N21/94 , G01N2201/1241
摘要： The detection part has: a subtraction module for calculating correction data from data of detection systems when a reference-voltage generation module applies a reference voltage to the detection systems; a data-holding module for holding the correction data; an addition module for making a correction of detection data; a comparison module for comparing the detection data with switching data; and a selector for switching data of the detection systems including data subjected to the correction according to the output of the comparison module.
摘要翻译：检测部具有：减法模块，用于当参考电压产生模块向检测系统施加参考电压时，从检测系统的数据计算校正数据; 用于保持校正数据的数据保持模块; 用于对检测数据进行校正的加法模块; 比较模块，用于将检测数据与切换数据进行比较; 以及选择器，用于根据比较模块的输出来切换包括经过校正的数据的检测系统的数据。

3. 发明授权

US07358953B2 Semiconductor device and testing method of semiconductor device 有权
标题翻译：半导体器件的半导体器件和测试方法
公开(公告)号：US07358953B2
公开(公告)日：2008-04-15
申请号：US10714943
申请日：2003-11-18
申请人： Masami Makuuchi , Kengo Imagawa , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai , Atsushi Obuchi
发明人： Masami Makuuchi , Kengo Imagawa , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai , Atsushi Obuchi
IPC分类号： G09G3/36
CPC分类号： G09G3/006 , G09G3/3648 , G09G5/006 , G09G5/39 , G09G2310/027 , Y10S345/904
摘要： A semiconductor device having a liquid crystal driving circuit is disclosed. The driving circuit includes a digital functional unit and an analog functional unit. The digital functional unit is comprised of a display controller and a display data storage RAM, while the analog functional unit is made up of a gradation voltage generating circuit and a gradation voltage selecting circuit. The digital and analog function units are functionally divided from each other and testing of the digital function and testing of the analog function unit are performed in an overlapping manner independently from each other.
摘要翻译：公开了一种具有液晶驱动电路的半导体器件。驱动电路包括数字功能单元和模拟功能单元。数字功能单元包括显示控制器和显示数据存储RAM，而模拟功能单元由灰度电压产生电路和灰度电压选择电路组成。数字和模拟功能单元在功能上彼此划分，并且以彼此独立的重叠方式执行数字功能的测试和模拟功能单元的测试。

4. 发明申请

US20050122300A1 Semiconductor device and testing method thereof 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US20050122300A1
公开(公告)日：2005-06-09
申请号：US10981715
申请日：2004-11-05
申请人： Masami Makuuchi , Norio Chujo , Kengo Imagawa , Ritsuro Orihashi , Yoshitomo Arai
发明人： Masami Makuuchi , Norio Chujo , Kengo Imagawa , Ritsuro Orihashi , Yoshitomo Arai
IPC分类号： G01R31/316 , G01R31/28 , G02F1/133 , G09G3/00 , G09G3/20 , G09G3/36 , H01L21/822 , H01L27/04
CPC分类号： G09G3/006 , G09G3/3688
摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.
摘要翻译：根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。因此，可以减少测试所需的时间和成本。

5. 发明授权

US07474290B2 Semiconductor device and testing method thereof 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US07474290B2
公开(公告)日：2009-01-06
申请号：US10981715
申请日：2004-11-05
申请人： Masami Makuuchi , Norio Chujo , Kengo Imagawa , Ritsuro Orihashi , Yoshitomo Arai
发明人： Masami Makuuchi , Norio Chujo , Kengo Imagawa , Ritsuro Orihashi , Yoshitomo Arai
IPC分类号： G09G3/36
CPC分类号： G09G3/006 , G09G3/3688
摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.
摘要翻译：根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。因此，可以减少测试所需的时间和成本。

6. 发明授权

US07443373B2 Semiconductor device and the method of testing the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US07443373B2
公开(公告)日：2008-10-28
申请号：US11002143
申请日：2004-12-03
申请人： Kengo Imagawa , Masami Makuuchi , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai
发明人： Kengo Imagawa , Masami Makuuchi , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/006 , G09G2310/0289
摘要： A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.
摘要翻译：包括在本申请中的发明中的一个解决的问题是提供一种半导体器件，其可以通过半导体测试设备的数量少于半导体器件的集成输出引脚的较少通道同时测试多个输出引脚。代表性的发明之一具有这样的结构，即作为具有驱动液晶显示面板的栅极线的功能的半导体器件的LCD驱动器包括：用于将正和负电压的极性反转的异或电路，驾驶门线; 能够改变和控制高阻抗状态的用于驱动栅极线的输出电路的三态逆变器电路; 以及用于控制异或电路和三态逆变器电路的测试控制端子TEST中的至少一个。当进行测试时，仅栅极输出的一个端子输出正电压VGH或负电压VGL，另一个端子被设置为高阻抗状态，从而同时测试多个栅极输出。

7. 发明申请

US20050122297A1 Semiconductor device and the method of testing the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US20050122297A1
公开(公告)日：2005-06-09
申请号：US11002143
申请日：2004-12-03
申请人： Kengo Imagawa , Masami Makuuchi , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai
发明人： Kengo Imagawa , Masami Makuuchi , Norio Chujo , Ritsuro Orihashi , Yoshitomo Arai
IPC分类号： G01R31/28 , G02F1/1345 , G09G3/00 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/006 , G09G2310/0289
摘要： A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.
摘要翻译：包括在本申请中的发明中的一个解决的问题是提供一种半导体器件，其可以通过半导体测试设备的数量少于半导体器件的集成输出引脚的较少通道同时测试多个输出引脚。代表性的发明之一具有这样的结构，即作为具有驱动液晶显示面板的栅极线的功能的半导体器件的LCD驱动器包括：用于将正和负电压的极性反转的异或电路，驾驶门线; 能够改变和控制高阻抗状态的用于驱动栅极线的输出电路的三态逆变器电路; 以及用于控制异或电路和三态逆变器电路的测试控制端子TEST中的至少一个。当进行测试时，仅栅极输出的一个端子输出正电压VGH或负电压VGL，另一个端子被设置为高阻抗状态，从而同时测试多个栅极输出。

8. 发明授权

US07668027B2 Semiconductor device, testing and manufacturing methods thereof 失效
标题翻译：半导体器件，其测试和制造方法
公开(公告)号：US07668027B2
公开(公告)日：2010-02-23
申请号：US11365492
申请日：2006-03-02
申请人： Kengo Imagawa , Masami Makuuchi , Ritsuro Orihashi , Yoshiharu Ikeda , Koichiro Eguchi
发明人： Kengo Imagawa , Masami Makuuchi , Ritsuro Orihashi , Yoshiharu Ikeda , Koichiro Eguchi
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.
摘要翻译：为了容易地对包括在半导体器件中的存储器接口执行定时测试以满足对等待时间的限制，本发明提供一种具有存储器接口的半导体器件，包括：时钟输出端子，其输出与连接到存储器接口的存储器的操作; 命令终端，其输出与所述存储器的状态的控制相关联的命令信号; 与存储器交换数据信号的数据终端; 以及数据选通端子，用于交换用于建立数据信号的数据选通信号。该半导体器件包括测试端子，其预先输出用于在命令信号之外的存储器接口上开始测试的信号。

9. 发明申请

US20070047345A1 Semiconductor device, testing and manufacturing methods thereof 失效
标题翻译：半导体器件，其测试和制造方法
公开(公告)号：US20070047345A1
公开(公告)日：2007-03-01
申请号：US11365492
申请日：2006-03-02
申请人： Kengo Imagawa , Masami Makuuchi , Ritsuro Orihashi , Yoshiharu Ikeda , Koichiro Eguchi
发明人： Kengo Imagawa , Masami Makuuchi , Ritsuro Orihashi , Yoshiharu Ikeda , Koichiro Eguchi
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.
摘要翻译：为了容易地对包括在半导体器件中的存储器接口执行定时测试以满足对等待时间的限制，本发明提供一种具有存储器接口的半导体器件，包括：时钟输出端子，其输出与连接到存储器接口的存储器的操作; 命令终端，其输出与所述存储器的状态的控制相关联的命令信号; 与存储器交换数据信号的数据终端; 以及数据选通端子，用于交换用于建立数据信号的数据选通信号。该半导体器件包括测试端子，其预先输出用于在命令信号之外的存储器接口上开始测试的信号。

10. 发明授权

US07816955B2 Ramp generator and circuit pattern inspection apparatus using the same ramp generator 有权
标题翻译：使用斜坡发生器的斜坡发生器和电路图案检查装置
公开(公告)号：US07816955B2
公开(公告)日：2010-10-19
申请号：US12044108
申请日：2008-03-07
申请人： Masayoshi Takahashi , Kengo Imagawa , Norio Chujo
发明人： Masayoshi Takahashi , Kengo Imagawa , Norio Chujo
IPC分类号： H03K4/06
CPC分类号： H03K4/06 , H01J37/1477 , H01J37/28 , H03K3/0231
摘要： The present invention provides a ramp generator capable of appropriately setting a rise starting point of an output voltage of a ramp waveform and an output voltage at the time of stable output. A current adjustment unit including a differential pair of transistors and an amplifier constitute a feedback circuit. By controlling the charging/discharging of an integration capacitor by ON/OFF of a discharge current source connected to a common emitter terminal of the current adjustment unit, an output of the ramp waveform outputted from an output terminal disposed at the connection end of the integration capacitor is controlled.
摘要翻译：本发明提供一种斜坡发生器，其能够适当地设定稳定输出时的斜坡波形的输出电压的上升起点和输出电压。包括差分对晶体管和放大器的电流调节单元构成反馈电路。通过连接到电流调节单元的公共发射极端子的放电电流源的ON / OFF来控制积分电容器的充电/放电，从设置在集成连接端的输出端子输出的斜坡波形的输出电容器被控制。

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