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1. 发明授权

US06372573B1 Self-aligned trench capacitor capping process for high density DRAM cells 有权
公开(公告)号：US06372573B1
公开(公告)日：2002-04-16
申请号：US09426754
申请日：1999-10-26
申请人： Masami Aoki , Hirofumi Inoue , Bruce W. Porth , Max G. Levy , Victor R. Nastasi , Emily E. Fisch , Paul C. Buschner
发明人： Masami Aoki , Hirofumi Inoue , Bruce W. Porth , Max G. Levy , Victor R. Nastasi , Emily E. Fisch , Paul C. Buschner
IPC分类号： H01L218242
摘要： A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

2. 发明授权

US07223697B2 Chemical mechanical polishing method 有权
标题翻译：化学机械抛光方法
公开(公告)号：US07223697B2
公开(公告)日：2007-05-29
申请号：US10710604
申请日：2004-07-23
申请人： Garth A. Brooks , Bruce W. Porth , Steven M. Shank , Eric J. White
发明人： Garth A. Brooks , Bruce W. Porth , Steven M. Shank , Eric J. White
IPC分类号： H01L21/302
CPC分类号： H01L27/10867 , H01L21/3212
摘要： A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.
摘要翻译：一种形成结构，结构阵列和存储单元的方法，制造结构的方法，包括：（a）在衬底中形成沟槽; （b）在所述衬底的表面上沉积第一层多晶硅，所述第一层多晶硅填充所述沟槽; （c）在第一温度下化学机械抛光所述第一层多晶硅以暴露所述衬底的表面; （d）从沟槽去除第一多晶硅的上部; （e）在所述衬底的表面上沉积第二层多晶硅，所述第二层多晶硅填充所述沟槽; 和（f）在第二温度下对所述第二层多晶硅进行化学机械抛光以暴露所述衬底的表面，所述第二温度不同于所述第一温度。

3. 发明授权

US07893479B2 Deep trench in a semiconductor structure 有权
标题翻译：半导体结构中的深沟槽
公开(公告)号：US07893479B2
公开(公告)日：2011-02-22
申请号：US12538193
申请日：2009-08-10
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号： H01L29/108
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.
摘要翻译：半导体结构。硬掩模层位于半导体衬底的顶部衬底表面上。硬掩模层包括硬掩模层开口，顶部衬底表面的一部分暴露于周围的环境中。硬掩模层包括在顶部衬底表面上的衬垫氧化物层，衬垫氧化物层上的氮化物层，在氮化物层的顶部上的BSG（硼硅酸盐玻璃）层，以及顶部上的ARC（抗反射涂层）的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。

4. 发明授权

US07303952B2 Method for fabricating doped polysilicon lines 有权
标题翻译：掺杂多晶硅生产线的制造方法
公开(公告)号：US07303952B2
公开(公告)日：2007-12-04
申请号：US10711771
申请日：2004-10-04
申请人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
发明人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

5. 发明授权

US07101806B2 Deep trench formation in semiconductor device fabrication 失效
标题翻译：半导体器件制造中的深沟槽形成
公开(公告)号：US07101806B2
公开(公告)日：2006-09-05
申请号：US10711953
申请日：2004-10-15
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
摘要翻译：一种用于蚀刻半导体衬底中的深沟槽的方法。该方法包括以下步骤：（a）在半导体衬底的顶部上形成硬掩模层，（b）蚀刻硬掩模层中的硬掩模开口，以通过硬掩模层开口将半导体衬底暴露于大气中其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤，以及（c）蚀刻硬掩模开口的底部的深沟槽基板通过硬掩模开口。

6. 发明申请

US20090294926A1 DEEP TRENCH IN A SEMICONDUCTOR STRUCTURE 有权
标题翻译： DEEP TRENCH在半导体结构中
公开(公告)号：US20090294926A1
公开(公告)日：2009-12-03
申请号：US12538193
申请日：2009-08-10
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号： H01L29/06
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.
摘要翻译：半导体结构。硬掩模层位于半导体衬底的顶部衬底表面上。硬掩模层包括硬掩模层开口，顶部衬底表面的一部分暴露于周围的环境中。硬掩模层包括在顶部衬底表面上的衬垫氧化物层，衬垫氧化物层上的氮化物层，在氮化物层的顶部上的BSG（硼硅酸盐玻璃）层，以及顶部上的ARC（抗反射涂层）的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。

7. 发明授权

US07573085B2 Deep trench formation in semiconductor device fabrication 失效
标题翻译：半导体器件制造中的深沟槽形成
公开(公告)号：US07573085B2
公开(公告)日：2009-08-11
申请号：US11458828
申请日：2006-07-20
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号： H01L27/108
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.
摘要翻译：半导体结构。该结构包括（a）半导体衬底; （b）半导体衬底上的硬掩模层; 和（c）在硬掩模层中开口的硬掩模层。半导体衬底通过硬掩模层开口暴露于大气。硬掩模层开口包括顶部和底部，其中底部设置在顶部和半导体衬底之间。底部具有比顶部更宽的横向宽度。

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