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1. 发明授权

US6091667A Semiconductor memory device and a data reading method and a data writing method therefor 失效
标题翻译：半导体存储器件及数据读取方法及其数据写入方法
公开(公告)号：US6091667A
公开(公告)日：2000-07-18
申请号：US120214
申请日：1998-07-21
申请人： Masahiro Tanaka , Hisatada Miyatake , Yolaro Mori , Noritoshi Yamasaki
发明人： Masahiro Tanaka , Hisatada Miyatake , Yolaro Mori , Noritoshi Yamasaki
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/41 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1006
摘要： A memory device to perform a plurality of data transfers during a single memory cycle without extending the cycle time for memory access, and to enhance the data transfer rate.A memory array 1 has a plurality of word lines, a plurality of bit lines divided into a predetermined number of groups, and a plurality of memory cells. The bit lines are grouped based on a residue obtained by dividing a column address designating a bit line by the number of groups. The column address decoder 4 generates column addresses of the group number in accordance with the column address signal and an access order signal designating the access order for the groups. When the access order signal designates the ascending order, the bit line selection means 3 generates sequential column addresses, in a number equivalent to the group number and in the ascending order, with the column address signal serving as a reference. When the access order signal designates the descending order, the bit line selection means 3 generates sequential column addresses, in a number equivalent to the group number and in a descending order, with the column address signal serving as a reference.
摘要翻译：一种用于在单个存储器循环期间执行多个数据传输而不延长用于存储器访问的周期时间并且增强数据传送速率的存储器件。存储器阵列1具有多个字线，分成预定数量的组的多个位线和多个存储单元。基于通过将指定位线的列地址除以组数而获得的残差来分组位线。列地址解码器4根据列地址信号和指定组的访问顺序的访问顺序信号来生成组号的列地址。当访问命令信号指定升序时，位线选择装置3以列地址信号作为基准，产生与组号等价的顺序列地址，并以升序生成顺序列地址。当存取指令信号指定降序时，位线选择装置3以列地址信号作为参考，以等于组号并按降序生成顺序列地址。

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