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    • 2. 发明授权
    • Circuit switching method and apparatus for time division network with
various transmission speeds
    • 具有各种传输速度的时分网络的电路交换方法和装置
    • US5197063A
    • 1993-03-23
    • US641928
    • 1991-01-16
    • Yukio NakanoTadayuki KannoMasahiro TakatoriHiromi Ueda
    • Yukio NakanoTadayuki KannoMasahiro TakatoriHiromi Ueda
    • H04J3/22H04J3/00H04J3/16H04Q11/04
    • H04Q11/04H04J3/1611
    • A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.
    • 一种用于具有各种传输速度的时分网络的电路交换装置和方法,用于对包括不同传输速度的信号的多个电路进行时分复用,将其发送到输入公路上,以预定的方式将数据存储器重复地记录发送的信号 以预定顺序将各个记录信号读出到输出高速公路上。 用于从数据存储器读取信号的访问单元具有用于存储电路切换信息的地址控制存储器,用于存储各个电路的传输速度信息的电路速度控制存储器和用于生成访问数据存储器的地址的地址生成部分 电路切换信息的基础和来自这些存储器的电路传输速度信息。
    • 3. 发明授权
    • Method of phase-converting frame and apparatus using same
    • 使用相位变换框架和装置的方法
    • US5128939A
    • 1992-07-07
    • US507506
    • 1990-04-11
    • Masahiro TakatoriYukio NakanoTadayuki KannoHiromi Ueda
    • Masahiro TakatoriYukio NakanoTadayuki KannoHiromi Ueda
    • H04J3/00H04J3/06H04L7/00
    • H04J3/0623
    • Disclosed is a method and apparatus of phase-converting a frame, each frame containing a plurality of data, a frame synchronous signal arranged in a predetermined first relative phase position in the frame, and a pointer arranged in a predetermined second relative phase position and storing a value indicating a phase difference between the second relative phase position and the front position of the data in the frame, in which the following operations are carried out: consecutively receiving the frames; sequentially arranging a predetermined number of data among the plurality of data in the received frame in a transmission frame in accordance with a received order, and arranging the frame synchronous signal and the pointer in the received frame in the first relative phase position and the second relative phase position, the first relative phase position being independent to the second relative phase position, to form the tansmission frame; detecting a fourth relative phase position in the transmission frame, the fourth relative phase position storing a data same as a specific data arranged in a third relative phase positon in the received frame; obtaining a difference between the fourth relative phase position and the third relative phase position; and setting the difference between the value of the pointer in the received frame and the obtained phase difference as the value of the pointer in the transmission frame.
    • 公开了一种帧相位转换的方法和装置,每帧包含多个数据,布置在帧中预定的第一相对相位位置的帧同步信号,以及布置在预定的第二相对相位位置的指针,并存储 指示执行以下操作的帧中的数据的第二相对位置与前端位置之间的相位差的值:连续接收帧; 根据接收到的顺序在传输帧中顺序排列接收到的帧中的多个数据中的预定数量的数据,并将帧同步信号和指针置于接收帧中的第一相对相位和第二相位 相位位置,第一相对相位位置独立于第二相对位置,以形成输出帧; 检测所述传输帧中的第四相对相位,所述第四相对相位位置存储与所述接收帧中的第三相位相位中布置的特定数据相同的数据; 获得所述第四相对位置与所述第三相对位置之间的差; 并且将接收到的帧中的指针的值与获得的相位差之间的差设置为发送帧中的指针的值。
    • 4. 发明授权
    • Frame aligner and method and system for control thereof
    • 框架对准器及其控制方法和系统
    • US5271006A
    • 1993-12-14
    • US663956
    • 1991-03-19
    • Yoshihiro AshiTadayuki KannoMasahiro TakatoriHiromi Ueda
    • Yoshihiro AshiTadayuki KannoMasahiro TakatoriHiromi Ueda
    • H04J3/06H04J3/22
    • H04J3/0629
    • A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.
    • PCT No.PCT / JP90 / 00925 Sec。 371日期1991年3月19日 102(e)1991年3月19日PCT PCT 1990年7月18日PCT公布。 公开号WO91 / 01601 日期1991年2月7日。一种帧对准器及其控制方法和系统,其中在确保TSSI(时隙序列完整性)的同时执行帧对准。 在用于发送具有高速帧中的帧结构的多个低速信号的系统中,设置用于帧对准器存储器的写入开始阶段的多个候选,并且通过访问存储写入的公共相位存储器 低速信号共享的起始相位需要存储在高速帧中的所有低速信号之间的相位匹配,从用于帧对准器存储器的写入开始相位的候选中选择写入开始相位。
    • 6. 发明授权
    • Routing method and apparatus for switching between routing and
conversion tables based on selection information included in cells to
be routed
    • 基于包括在要路由的单元中的选择信息,在路由和转换表之间切换的路由方法和装置
    • US5473598A
    • 1995-12-05
    • US744513
    • 1991-08-13
    • Masahiro TakatoriYukio NakanoYoshihiro AshiTadayuki Kanno
    • Masahiro TakatoriYukio NakanoYoshihiro AshiTadayuki Kanno
    • H04L12/70H04L12/931H04L12/947H04J3/26
    • H04L49/254H04L49/256H04L49/3009H04L49/3081H04L49/309H04L49/552H04L2012/5627
    • A cell routing method and apparatus in an ATM processing apparatus. The ATM processing apparatus has two or more routing tables associated with address filters of an ATM switch to store routing information for indicating the destination of cell output, and two or more conversion tables associated with VPI conversion circuits for replacing VPI (Virtual Path Identifier) or VCI conversion circuits for replacing VCI (Virtual Channel Identifier) to store information for indicating the VPI or VCI obtained after conversion. In an input interface circuit, selection information indicating which routing table and conversion table out of the above described two or more routing tables and two or more conversion tables should be selected is written into an occupied area within a cell. In a switch circuit, the selection information is read and one routing table is selected out of the above described two or more routing tables on the basis of the selection information thus read, and cell routing is thus performed based on information in the selected routing table. Further, in an output interface circuit, selection information contained in the cell is read and one conversion table is selected out of the above described two or more conversion tables on the basis of the selection information thus read, and VPI conversion or VCI conversion is thus executed based on information in the selected conversion table.
    • 一种ATM处理装置中的小区路由方法和装置。 ATM处理装置具有与ATM交换机的地址过滤器相关联的两个或多个路由表,以存储用于指示小区输出的目的地的路由信息​​,以及与用于替换VPI(虚拟路径标识符)的VPI转换电路相关联的两个或更多个转换表, 用于替换VCI(虚拟信道标识符)的VCI转换电路以存储用于指示转换后获得的VPI或VCI的信息。 在输入接口电路中,指示应当选择上述两个或多个路由表和两个或多个转换表中的哪个路由表和转换表的选择信息被写入小区内的占用区域。 在开关电路中,读取选择信息,并且根据这样读取的选择信息,从上述两个或多个路由表中选出一个路由表,并且基于所选择的路由表中的信息执行小区路由 。 此外,在输出接口电路中,读取包含在单元中的选择信息,并且根据这样读取的选择信息从上述两个或更多个转换表中选出一个转换表,并且因此进行VPI转换或VCI转换 基于所选转换表中的信息执行。