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1. 发明申请

US20120057111A1 LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置
公开(公告)号：US20120057111A1
公开(公告)日：2012-03-08
申请号：US13224476
申请日：2011-09-02
申请人： Masahiro OHKUBO , Koichi Igeta , Go Saitou , Katsuhiro Kato
发明人： Masahiro OHKUBO , Koichi Igeta , Go Saitou , Katsuhiro Kato
IPC分类号： G02F1/1339 , G02F1/1335
CPC分类号： G02F1/13394 , G02F1/133514 , G02F1/1339 , G02F2001/133519
摘要： The liquid crystal display device according to the present invention is a liquid crystal display device provided with a liquid crystal display panel having; a first substrate; a second substrate; a sealing material provided between the first substrate and the second substrate so that the first substrate and the second substrate are pasted together; and a liquid crystal layer sealed in the region surrounded by the sealing material between the first substrate and the second substrate, wherein the second substrate has a color filter and a protective film for covering the color filter on the surface of the second substrate on the liquid crystal layer side, and an end of the protective film is located inside an end of the second substrate and between the two sides of the sealing material, which are opposite to each other (outer wall surface and inner wall surface).
摘要翻译：根据本发明的液晶显示装置是具有液晶显示面板的液晶显示装置，第一衬底; 第二基板; 设置在第一基板和第二基板之间的密封材料，使得第一基板和第二基板被粘贴在一起; 以及密封在由所述第一基板和所述第二基板之间的密封材料包围的区域中的液晶层，其中所述第二基板具有滤色器和用于在所述液体上的所述第二基板的表面上覆盖所述滤色器的保护膜晶体层侧，并且保护膜的端部位于第二基板的端部内部，并且彼此相对的密封材料的两侧（外壁表面和内壁表面）之间。

2. 发明授权

US08730445B2 Liquid crystal display device with first and second substrates sealed by sealing material with an end of protective material on second substrate being disposed between inner and outer wall surfaces of the sealing material 有权
标题翻译：具有第一和第二基板的液晶显示装置设置在密封材料的内壁和外壁之间，该密封材料用第二基板上的保护材料的端部密封
公开(公告)号：US08730445B2
公开(公告)日：2014-05-20
申请号：US13224476
申请日：2011-09-02
申请人： Masahiro Ohkubo , Koichi Igeta , Go Saitou , Katsuhiro Kato
发明人： Masahiro Ohkubo , Koichi Igeta , Go Saitou , Katsuhiro Kato
IPC分类号： G02F1/1339 , G02F1/1335 , G02F1/1333 , G02F1/1343 , G02F1/1337
CPC分类号： G02F1/13394 , G02F1/133514 , G02F1/1339 , G02F2001/133519
摘要： The liquid crystal display device according to the present invention is a liquid crystal display device provided with a liquid crystal display panel having: a first substrate; a second substrate; a sealing material provided between the first substrate and the second substrate so that the first substrate and the second substrate are pasted together; and a liquid crystal layer sealed in the region surrounded by the sealing material between the first substrate and the second substrate, wherein the second substrate has a color filter and a protective film for covering the color filter on the surface of the second substrate on the liquid crystal layer side, and an end of the protective film is located inside an end of the second substrate and between the two sides of the sealing material, which are opposite to each other (outer wall surface and inner wall surface).
摘要翻译：根据本发明的液晶显示装置是具有液晶显示面板的液晶显示装置，具有：第一基板; 第二基板; 设置在第一基板和第二基板之间的密封材料，使得第一基板和第二基板被粘贴在一起; 以及密封在由所述第一基板和所述第二基板之间的密封材料包围的区域中的液晶层，其中所述第二基板具有滤色器和用于在所述液体上的所述第二基板的表面上覆盖所述滤色器的保护膜晶体层侧，并且保护膜的端部位于第二基板的端部内部，并且彼此相对的密封材料的两侧（外壁表面和内壁表面）之间。

3. 发明授权

US07649229B2 ESD protection device 有权
标题翻译： ESD保护装置
公开(公告)号：US07649229B2
公开(公告)日：2010-01-19
申请号：US11730081
申请日：2007-03-29
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01L23/60
CPC分类号： H01L27/0266 , H01L29/41725 , H01L29/4238 , H01L29/456 , H01L29/78
摘要： A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.
摘要翻译：一种能够在不增加泄漏电流的情况下防止静电浪涌的半导体器件。在半导体器件中，在源极线和接地线之间设置有用于保护内部电路的保护电路。保护电路具有保护晶体管，漏极连接到源极线，源极和栅极连接到地线。保护晶体管通过一体地形成两种晶体管结构部分而构成。晶体管结构部分中的后者在栅极长度上比其前者长。此外，后一晶体管结构部分的栅极宽度之和大于前一晶体管结构部分的栅极宽度之和。

4. 发明授权

US07061052B2 Input protection circuit connected to protection circuit power source potential line 有权
公开(公告)号：US07061052B2
公开(公告)日：2006-06-13
申请号：US10323912
申请日：2002-12-20
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01L23/62
CPC分类号： H01L27/0292 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An input protection circuit capable of precisely bypassing a surge current to a power source terminal and protecting the gate of a protective transistor from an electrostatic surge. The input protection circuit has an input terminal which receives an input signal, a first power source terminal which receives a first power source electric potential, and a first protective power source potential line connected to the first power source terminal for supplying the first power source electric potential to an input protection circuit. The input protection circuit has a first input protection transistor of a first conductive type having a drain connected to the input terminal, a gate and a source connected to the first protective power source potential line. Moreover, the input protection circuit has a second input protection transistor of the first conductive type having a drain connected to an input terminal of an internal circuit, a gate connected to the input terminal via a protective resistor, and a source connected to the first protective power source potential line.

5. 发明授权

US06861010B2 COPPER-BASED METAL POLISHING COMPOSITION, METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, POLISHING COMPOSITION, ALUMINUM-BASED METAL POLISHING COMPOSITION, AND TUNGSTEN-BASED METAL POLISHING COMPOSITION 有权
标题翻译：基于铜的金属抛光组合物，制造半导体器件的方法，抛光组合物，基于铝的金属抛光组合物和基于金属的金属抛光组合物
公开(公告)号：US06861010B2
公开(公告)日：2005-03-01
申请号：US10124423
申请日：2002-04-18
申请人： Hideaki Hirabayashi , Naoaki Sakurai , Toshitsura Cho , Shumpei Shimizu , Katsuhiro Kato , Akiko Saito
发明人： Hideaki Hirabayashi , Naoaki Sakurai , Toshitsura Cho , Shumpei Shimizu , Katsuhiro Kato , Akiko Saito
IPC分类号： B24B37/00 , C09G1/02 , C09K3/14 , C09K13/00 , C09K13/06 , H01L21/302 , H01L21/304 , H01L21/3205 , H01L21/321 , H01L21/461 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/3212 , C09G1/02
摘要： The copper-based metal polishing composition causes Cu or Cu alloy not to be dissolved at all in immersing Cu or Cu alloy therein, and makes it possible to polish Cu or Cu alloy at a high rate in polishing treatment. Such a copper-based metal polishing composition comprises a water-soluble first organic acid capable of reaction with copper to produce a copper complex compound which is substantially insoluble in water and has a mechanical strength lower than that of copper, at least one second organic acid selected from an organic acid having a single carboxyl group and a single hydroxyl group and oxalic acid, an abrasive grain, an oxidizing agent, and water.
摘要翻译：铜基金属抛光组合物使Cu或Cu合金在其中浸没Cu或Cu合金时根本不溶解，并且可以在抛光处理中高速抛光Cu或Cu合金。这种铜基金属抛光组合物包含能够与铜反应的水溶性第一有机酸，以产生基本上不溶于水的机械强度低于铜的机械强度的铜络合物，至少一种第二有机酸选自具有单个羧基和单个羟基的有机酸和草酸，磨料颗粒，氧化剂和水。

6. 发明授权

US06710991B2 Electrostatic-breakdown-preventive and protective circuit for semiconductor-device 有权
标题翻译：半导体器件的防静电和保护电路
公开(公告)号：US06710991B2
公开(公告)日：2004-03-23
申请号：US10305954
申请日：2002-11-29
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H02H320
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations. In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the invention, a protective transistor is provided between a power-source line and a ground line for an input/output circuit, a position between a power-source line and ground line for a circuit block A, a position between a power-source line and a ground line for a circuit block B, and a position between a power-source line and a ground line for an input/output circuit. A PMOS protective transistor is provided between the power-source line for the circuit block A and the power-source line for the circuit block B, and an NMOS protective transistor is provided between the ground lines in an internal-circuit region in the vicinity of a signal line (protective resistor).
摘要翻译：本发明提供一种能够执行高速操作的用于半导体器件的紧凑型防静电和保护电路。在本发明的半导体装置用静电防止和保护电路中，在电源线和输入输出电路的接地线之间设置保护晶体管，电源线与电源线之间的位置用于电路块A的接地线，用于电路块B的电源线和接地线之间的位置，以及用于输入/输出电路的电源线和接地线之间的位置。在电路块A的电源线和电路块B的电源线之间设置PMOS保护晶体管，并且NMOS保护晶体管设置在接地线之间的内部电路区域信号线（保护电阻）。

7. 发明授权

US06654078B1 Liquid crystal module mounting structure and mobile terminal mounted with the same 有权
标题翻译：液晶模块安装结构和移动终端安装相同
公开(公告)号：US06654078B1
公开(公告)日：2003-11-25
申请号：US09505965
申请日：2000-02-17
申请人： Katsuhiro Kato , Masatake Baba , Michiaki Nishiyama , Fumihiko Fujishiro , Takakazu Yano , Toshihisa Ogawa , Tomoo Miwa , Yasuhiro Sato
发明人： Katsuhiro Kato , Masatake Baba , Michiaki Nishiyama , Fumihiko Fujishiro , Takakazu Yano , Toshihisa Ogawa , Tomoo Miwa , Yasuhiro Sato
IPC分类号： G02F11333
CPC分类号： G06F1/1637 , G02F1/133308 , G02F2201/465 , G02F2202/28 , G06F1/1616
摘要： The present invention provides a mounting structure for mounting a liquid crystal module to a cover of a mobile terminal. The mounting structure comprises: at least a pair of first and second engagement parts, wherein the first engagement part is provided on a side portion of the liquid crystal module, whilst the second engagement part is provided on a side portion of a structural member of the cover, so that the paired first and second engagement parts are engaged with each other only by fitting the liquid crystal module into the structural member of the cover.
摘要翻译：本发明提供了一种用于将液晶模块安装到移动终端的盖的安装结构。安装结构包括：至少一对第一和第二接合部分，其中第一接合部分设置在液晶模块的侧部上，而第二接合部分设置在液晶组件的结构部件的侧部上使得成对的第一和第二接合部分仅通过将液晶模块装配到盖的结构构件中而彼此接合。

8. 发明授权

US06534831B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06534831B2
公开(公告)日：2003-03-18
申请号：US09811391
申请日：2001-03-20
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01L2972
CPC分类号： H01L29/78639 , H01L27/1203
摘要： A trench 312a passing through an impurity area 301a of a circuit element formed at a semiconductor layer 306 of an SOI substrate 314 and extending to a conductive layer 311 formed at a semiconductor substrate 304 is provided. Inside the trench 312a, a conductor 310a for electrically connecting the impurity area 301a of the circuit element and the conductive layer 311 is formed. By adopting this structure, it becomes possible to promptly transmit a surge voltage applied through an external connector terminal 101 to the semiconductor substrate 304 to prevent breakdown at the buried insulator layer. Thus, the buried insulator layer in a semiconductor integrated circuit device having an SOI structure is protected by providing a protective element under the impurity area of the integrated circuit element to assure a high degree of reliability while enabling high-speed drive and higher integration.
摘要翻译：提供穿过形成在SOI衬底314的半导体层306并延伸到形成在半导体衬底304上的导电层311的电路元件的杂质区域301a的沟槽312a。在沟槽312a的内部，形成用于电连接电路元件的杂质区域301a和导电层311的导体310a。通过采用这种结构，可以将通过外部连接器端子101施加的浪涌电压迅速发送到半导体衬底304，以防止在埋层绝缘体层处的击穿。因此，通过在集成电路元件的杂质区域下方设置保护元件来保护具有SOI结构的半导体集成电路器件中的掩埋绝缘体层，以确保高可靠性，同时实现高速驱动和更高集成度。

9. 发明授权

US06267131B1 Method of controlling pressure in a chamber, apparatus for the same, and exposure apparatus 有权
标题翻译：控制室内压力的方法及其设备及曝光装置
公开(公告)号：US06267131B1
公开(公告)日：2001-07-31
申请号：US09594345
申请日：2000-06-15
申请人： Mutsuo Masada , Masao Nakata , Masahiro Shiraishi , Makoto Ogawa , Katsuhiro Kato , Yukiharu Okubo
发明人： Mutsuo Masada , Masao Nakata , Masahiro Shiraishi , Makoto Ogawa , Katsuhiro Kato , Yukiharu Okubo
IPC分类号： G05D1620
CPC分类号： G05D16/2013 , Y10T137/0379 , Y10T137/0396 , Y10T137/2012 , Y10T137/4673 , Y10T137/7501 , Y10T137/7761
摘要： A method of controlling pressure in a chamber, wherein the pressure in a chamber in which measurement such as laser measurement is conducted is maintained at a set pressure with respect to fluctuations in external atmospheric pressure, characterized by comprising: detecting the external atmospheric pressure, obtaining a long-term flat pressure value with respect to short time fluctuations of the detected external atmospheric pressure, creating a set pressure in the chamber by adding a predetermined pressure to the obtained pressure value, and detecting the pressure in the chamber while introducing external air so that the pressure in the chamber reaches the set pressure.
摘要翻译：一种控制室内的压力的方法，其中进行诸如激光测量的测量的室中的压力相对于外部大气压的波动保持在设定压力，其特征在于包括：检测外部大气压力，获得相对于检测到的外部大气压力的短时间波动的长期平坦压力值，通过向所获得的压力值添加预定压力来产生室内的设定压力，并且在引入外部空气的同时检测腔室中的压力室内的压力达到设定压力。

10. 发明授权

US08093629B2 Semiconductor chip and semiconductor device having a plurality of semiconductor chips 有权
标题翻译：具有多个半导体芯片的半导体芯片和半导体器件
公开(公告)号：US08093629B2
公开(公告)日：2012-01-10
申请号：US12193874
申请日：2008-08-19
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01L27/10 , H01L29/74 , H01L31/111 , H01L23/62
CPC分类号： H01L23/50 , H01L23/60 , H01L25/065 , H01L2224/48227 , H01L2924/13091 , H01L2924/00
摘要： The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided.
摘要翻译：本发明包括半导体芯片和具有多个半导体芯片的半导体器件，其在半导体芯片是多芯片封装的情况下不会增加芯片面积而能够从另一半导体芯片ESD保护，而不浪费芯片面积半导体芯片不是多芯片封装的。本发明的示例性半导体芯片包括内部电路和电连接到第一半导体芯片的接地总线的第一电极焊盘，其中电极焊盘提供并接收内部操作所需的电信号的区域电路，不能提供。

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