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1. 发明授权

US06292926B1 Functional module model, pipelined circuit synthesis and pipelined circuit device 失效
标题翻译：功能模块模型，流水线电路合成和流水线电路设备
公开(公告)号：US06292926B1
公开(公告)日：2001-09-18
申请号：US09109042
申请日：1998-07-02
申请人： Masahiro Fukui , Masakazu Tanaka , Toshiro Akino , Masaharu Imai , Yoshinori Takeuchi
发明人： Masahiro Fukui , Masakazu Tanaka , Toshiro Akino , Masaharu Imai , Yoshinori Takeuchi
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F7/5312 , G06F7/5443 , G06F2207/3884
摘要： The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.
摘要翻译：本发明提供了一种实现最佳流水线功能的模块模型。功能模块模型包括表示对应于可以插入流水线寄存器的位置的分割线的分割线数据，以及表示延迟与由分割线划分的每个分割区域的区域之间的权衡关系的延迟/面积数据。通过使用该功能模块模型，在由分割线数据表示的分割线之间选择流水线寄存器插入位置，并且基于由延迟表示的权衡关系来设置每个划分区域的延迟和面积 /区域数据。因此，可以合成具有最小面积的流水线电路。

2. 发明授权

US6026228A Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus 失效
标题翻译：集成电路设计方法，集成电路设计数据库设备和集成电路设计支持设备
公开(公告)号：US6026228A
公开(公告)日：2000-02-15
申请号：US989425
申请日：1997-12-12
申请人： Masaharu Imai , Akichika Siomi , Yoshinori Takeuchi , Jun Sato
发明人： Masaharu Imai , Akichika Siomi , Yoshinori Takeuchi , Jun Sato
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5045
摘要： In a database, variety of modules which can be used as constituent elements of the object of design are registered as parametrized models, and instance generating information representing a procedure of generating instances and feature estimation information representing a method for estimating design features are stored every abstraction level for the various modules. A floorplan oriented design is executed by means of the database. That is, even at the higher level of the behavior or RT level, by means of the database, the design features of each module to be used for the design are estimated and the floorplan is executed. On the basis of the execution result, the design features of the circuit scale, delay time, power consumption and so forth of the object of design are estimated, and it is decided whether or not a design change is required.
摘要翻译：在数据库中，将可用作设计对象的组成元素的各种模块作为参数化模型进行注册，并且生成表示生成实例的过程的信息的实例和表示用于估计设计特征的方法的特征估计信息的实例被存储在每个抽象级别为各种模块。通过数据库执行面向平面图的设计。也就是说，即使在较高级别的行为或RT级别，通过数据库，估计用于设计的每个模块的设计特征，并执行平面图。在执行结果的基础上，估计设计对象的电路规模，延迟时间，功耗等的设计特征，决定是否需要设计变更。

3. 发明申请

US20130061115A1 ERROR-CORRECTING CODE PROCESSING METHOD AND DEVICE 有权
标题翻译：错误修正代码处理方法和设备
公开(公告)号：US20130061115A1
公开(公告)日：2013-03-07
申请号：US13697576
申请日：2011-05-11
申请人： Masaharu Imai , Yoshinori Takeuchi , Keishi Sakanushi , Takashi Hamabe , Kazuki Ohya , Masaaki Abe
发明人： Masaharu Imai , Yoshinori Takeuchi , Keishi Sakanushi , Takashi Hamabe , Kazuki Ohya , Masaaki Abe
IPC分类号： G06F11/10 , H03M13/15
CPC分类号： H03M13/19 , H03M13/05 , H03M13/09 , H03M13/11 , H03M13/353 , H03M13/616 , H03M13/618 , H03M13/6502
摘要： An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.
摘要翻译：纠错码处理方法包括：计算下降符号或上升符号或两者，并且计算信息符号序列的所有元素的奇偶校验异或; 对下降符号的每个元素计算异或的一个或两个，以产生下降符号的低阶n位并且计算上升符号的每个元素的异或，以生成上升符号的低阶n位; 通过从降序排列的元素序列中按顺序选择元素，生成下降符号的高阶m位，并计算通过选择所得到的元素的异或来获得的元素中的一个或两个从元素序列上升序列，生成上升符号的高位m位; 并输出下行符号或上升符号或两者作为检查符号或综合征。

4. 发明授权

US09166624B2 Error-correcting code processing method and device 有权
标题翻译：纠错码处理方法和装置
公开(公告)号：US09166624B2
公开(公告)日：2015-10-20
申请号：US13697576
申请日：2011-05-11
申请人： Masaharu Imai , Yoshinori Takeuchi , Keishi Sakanushi , Takashi Hamabe , Kazuki Ohya , Masaaki Abe
发明人： Masaharu Imai , Yoshinori Takeuchi , Keishi Sakanushi , Takashi Hamabe , Kazuki Ohya , Masaaki Abe
IPC分类号： H03M13/09 , H03M13/19 , H03M13/35 , H03M13/00 , H03M13/05 , H03M13/11 , H03M13/53
CPC分类号： H03M13/19 , H03M13/05 , H03M13/09 , H03M13/11 , H03M13/353 , H03M13/616 , H03M13/618 , H03M13/6502
摘要： An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.
摘要翻译：纠错码处理方法包括：计算下降符号或上升符号或两者，并且计算信息符号序列的所有元素的奇偶校验异或; 对下降符号的每个元素计算异或的一个或两个，以产生下降符号的低阶n位并且计算上升符号的每个元素的异或，以生成上升符号的低阶n位; 通过从降序排列的元素序列中按顺序选择元素，生成下降符号的高阶m位，并计算通过选择所得到的元素的异或来获得的元素中的一个或两个从元素序列上升序列，生成上升符号的高位m位; 并输出下行符号或上升符号或两者作为检查符号或综合征。

5. 发明授权

US4573077A Solid state image sensing device with photometry function 失效
标题翻译：具有光度测量功能的固态摄像装置
公开(公告)号：US4573077A
公开(公告)日：1986-02-25
申请号：US647170
申请日：1984-09-04
申请人： Masaharu Imai
发明人： Masaharu Imai
IPC分类号： H01L27/146 , H04N5/235 , H04N5/335 , H04N5/351 , H04N5/353 , H04N5/378
CPC分类号： H04N3/1556 , H04N5/2351 , H04N5/2353
摘要： A solid state image sensing device having an array of pixels each including a static induction transistor and a capacitance connected to a gate thereof, a signal readout line connected to sources of the static induction transistors, a first scanning circuit for reading image signals out of the pixels successively in a destructive manner, a second scanning circuit for reading photometry signals out of preselected pixels in a non-destructive manner, an integrating circuit for integrating the photometry signals, a comparison circuit for comparing an integrated value with a predetermined value to produce a detection signal when the integrated value becomes equal to the predetermined value and a control circuit for controlling the first and second scanning circuits in accordance with the detection signal. When the detection signal is produced, the second scanning circuit is stopped and at the same time the first scanning circuit is initiated to readout all the pixels in a destructive manner.
摘要翻译：一种固态图像感测装置，具有各自包括静电感应晶体管和连接到其栅极的电容的像素阵列，连接到静态感应晶体管的源极的信号读出线，用于从静电感应晶体管的外部读取图像信号的第一扫描电路像素，以破坏性方式连续地进行扫描;第二扫描电路，用于以非破坏性方式从预选像素中读出测光信号;积分电路，用于积分测光信号;比较电路，用于将积分值与预定值进行比较，当积分值等于预定值时的检测信号和用于根据检测信号控制第一和第二扫描电路的控制电路。当产生检测信号时，第二扫描电路停止，并且同时启动第一扫描电路以以破坏性方式读出所有像素。

6. 发明授权

US4890308A Scanning pulse generating circuit 失效
标题翻译：扫描脉冲发生电路
公开(公告)号：US4890308A
公开(公告)日：1989-12-26
申请号：US240667
申请日：1988-09-06
申请人： Masaharu Imai
发明人： Masaharu Imai
IPC分类号： H03K5/15
CPC分类号： H03K5/15093
摘要： A scanning pulse generating circuit has a multiplicity of stages constitued by first basic circuits and second basic circuits which are connected to appear alternatingly in a cascade manner. The first basic circuit is composed of three or four MOS transistors and a feedback capacitor, and includes at least a bootstrap inverter, so as to produce predetermined output pulses upon receipt of driving synchronizing pulses. The second basic circuit has the same construction as the first basic circuit except that it receives different driving synchronizing pulse from that used in the first basic circuit. The output pulses from the respective basic circuits are free from drop of voltage and fluctuation, by virtue of the bootstrap effect. In addiition, power consumption can be reduced without difficulty.
摘要翻译：扫描脉冲发生电路具有通过第一基本电路和第二基本电路构成的多个级，所述第一基本电路和第二基本电路以级联方式交替显示。第一基本电路由三个或四个MOS晶体管和反馈电容器组成，并且至少包括自举逆变器，以便在接收到驱动同步脉冲时产生预定的输出脉冲。第二基本电路具有与第一基本电路相同的结构，除了它接收与第一基本电路中使用的不同的驱动同步脉冲。由于自举效应，各基本电路的输出脉冲没有电压和波动的下降。另外，功耗可以毫无困难地降低。

7. 发明授权

US4586084A Solid state image sensor 失效
标题翻译：固态图像传感器
公开(公告)号：US4586084A
公开(公告)日：1986-04-29
申请号：US758790
申请日：1985-07-25
申请人： Masaharu Imai
发明人： Masaharu Imai
IPC分类号： H01L27/146 , H04N5/335 , H04N5/359 , H04N3/12
CPC分类号： H04N3/1512
摘要： A solid state image sensor including a number of pixels arranged in a matrix form between row lines and column lines, successive pixels being readout by an XY address method to derive an image signal, each pixel being formed by a normally-on type static induction transistor and a vertical type control transistor having a source-drain passage connected to a gate of the static induction transistor, the vertical type control transistor being selectively made conductive during a horizontal blanking period to discharge an excess amount of photocarriers stored in the gate of static induction transistor through the source-drain passage. Since the vertical type control electrode assumes only a very small surface area, the packing density of pixels can be increased materially.
摘要翻译：一种固态图像传感器，包括在行线和列线之间以矩阵形式布置的多个像素，通过XY寻址方法读出连续像素以导出图像信号，每个像素由常开型静电感应晶体管以及具有连接到静电感应晶体管的栅极的源极 - 漏极通道的垂直型控制晶体管，垂直型控制晶体管在水平消隐期间选择性导通，以放电存储在静态感应栅极中的过量光载流子晶体管通过源极 - 漏极通道。由于垂直型控制电极仅具有非常小的表面积，所以可以大幅提高像素的堆积密度。

8. 发明授权

US4518863A Static induction transistor image sensor with noise reduction 失效
标题翻译：静电感应晶体管图像传感器具有降噪功能
公开(公告)号：US4518863A
公开(公告)日：1985-05-21
申请号：US397915
申请日：1982-07-13
申请人： Kenji Fukuoka , Masatoshi Ida , Atsuo Goto , Toshimasa Akagi , Masaharu Imai , Kenji Kimura
发明人： Kenji Fukuoka , Masatoshi Ida , Atsuo Goto , Toshimasa Akagi , Masaharu Imai , Kenji Kimura
IPC分类号： H01L27/146 , H04N5/335 , H04N5/353 , H04N5/355 , H04N5/365 , H04N5/374 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14679 , H04N5/2173
摘要： A SIT (Static Induction Transistor) image sensor with a high-sensitivity and a high-fidelity is disclosed. The image sensor comprises a SIT image cell array and a scanning circuit which scans in turn a plurality of SIT image cells in such a manner that respective scanning time in all the cells are equal throughout a sequential scanning operation for the SIT image sensor. A reading line and a refreshing line may be combined into a single line. A differential amplifier is provided for correcting a picture element information to remove a noise component therefrom.
摘要翻译：公开了具有高灵敏度和高保真度的SIT（静电感应晶体管）图像传感器。图像传感器包括SIT图像单元阵列和扫描电路，扫描电路依次扫描多个SIT图像单元，使得在整个单元中的相应扫描时间在SIT图像传感器的顺序扫描操作中相等。阅读线和刷新线可以组合成单行。提供了一种用于校正图像元素信息以从其中去除噪声分量的差分放大器。

9. 发明授权

US4636865A Solid state image sensor 失效
标题翻译：固态图像传感器
公开(公告)号：US4636865A
公开(公告)日：1987-01-13
申请号：US720805
申请日：1985-04-08
申请人： Masaharu Imai
发明人： Masaharu Imai
IPC分类号： H01L27/14 , H01L27/146 , H04N5/335 , H04N5/369 , H04N3/12
CPC分类号： H01L27/14679 , H04N3/1568
摘要： A solid state image sensor including a number of pixels arranged in a matrix form between row lines and column lines, successive pixels being read out by an XY address method to derive an image signal, each pixel being formed by a normally-on type static induction transistor and a control transistor having a source-drain passage connected to a gate of the static induction transistor, the control transistor being selectively made conductive during a horizontal blanking period to discharge an excess amount of photocarriers stored in the gate of static induction transistor through the source-drain passage.
摘要翻译：一种固态图像传感器，包括在行线和列线之间以矩阵形式布置的多个像素，通过XY地址方法读出连续像素以导出图像信号，每个像素由正常型静电感应晶体管和具有连接到静态感应晶体管的栅极的源极 - 漏极通路的控制晶体管，所述控制晶体管在水平消隐期间选择性导通，以通过所述晶体管通过所述静态感应晶体管的栅极中存储的过量的光载流子源漏通道。

10. 发明授权

US4611221A Solid state image pick-up device 失效
标题翻译：固态摄像装置
公开(公告)号：US4611221A
公开(公告)日：1986-09-09
申请号：US500303
申请日：1983-06-02
申请人： Masaharu Imai , Ikuo Tohukuji , Osamu Onitsuka , Terumasa Morita , Shunpei Tanaka , Hiroshi Matsui
发明人： Masaharu Imai , Ikuo Tohukuji , Osamu Onitsuka , Terumasa Morita , Shunpei Tanaka , Hiroshi Matsui
IPC分类号： H01L21/339 , H01L27/146 , H01L27/148 , H01L29/762 , H01L29/768 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/372 , H04N5/374 , H01L27/14
CPC分类号： H01L29/76816 , H01L27/14831
摘要： A solid state image pick-up device comprises a charge storage section for storing the charge corresponding to an image pattern, and a read-out section for reading out the stored charge in this charge storage section. The read-out section is connected to an output of the charge storage section and has a junction type field effect transistor to read out the stored charge as a picture signal.
摘要翻译：固态图像拾取装置包括用于存储对应于图像图案的电荷的电荷存储部分和用于读出该电荷存储部分中存储的电荷的读出部分。读出部分连接到电荷存储部分的输出，并具有结型型场效应晶体管，用于读出存储的电荷作为图像信号。

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