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1. 发明申请

US20050134533A1 Sustain driver, sustain control system, and plasma display 有权
标题翻译：维持驱动器，维持控制系统和等离子显示器
公开(公告)号：US20050134533A1
公开(公告)日：2005-06-23
申请号：US10991243
申请日：2004-11-17
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： G09G3/20 , G09G3/291 , G09G3/294 , G09G3/296 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H03K17/687 , G09G3/28
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

2. 发明授权

US07969429B2 Sustain driver, sustain control system, and display device 有权
标题翻译：维持驱动器，维持控制系统和显示设备
公开(公告)号：US07969429B2
公开(公告)日：2011-06-28
申请号：US11941240
申请日：2007-11-16
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： H01L29/739 , H01L31/00 , H03F3/16 , G09G3/28 , G09G5/00 , G06F3/038 , H01L27/10 , H01L29/73 , H03F3/04 , G09G3/20
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

3. 发明授权

US07358968B2 Sustain driver, sustain control system, and plasma display 有权
标题翻译：维持驱动器，维持控制系统和等离子显示器
公开(公告)号：US07358968B2
公开(公告)日：2008-04-15
申请号：US10991243
申请日：2004-11-17
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： H01L29/739 , H01L31/00 , H03F3/16 , G09G3/28 , G09G5/00 , G06F3/038 , H01L27/10 , H01L29/73 , H03F3/04 , G09G3/20
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

4. 发明申请

US20080068368A1 Sustain Driver, Sustain Control System, And Display Device 有权
标题翻译：维持驱动器，维护控制系统和显示设备
公开(公告)号：US20080068368A1
公开(公告)日：2008-03-20
申请号：US11941240
申请日：2007-11-16
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： G09G3/28 , G09G5/00
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

5. 发明授权

US07495296B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07495296B2
公开(公告)日：2009-02-24
申请号：US11139590
申请日：2005-05-31
申请人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
发明人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
IPC分类号： H01L29/94
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.
摘要翻译：本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路，驱动器，使得每个单元排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度，第二电平移位电路和预驱动器对应于低侧晶体管的单元宽度。

6. 发明申请

US20050263910A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050263910A1
公开(公告)日：2005-12-01
申请号：US11139590
申请日：2005-05-31
申请人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
发明人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
IPC分类号： H01L23/528 , H01L27/118 , H01L23/52
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize the output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of the cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, where a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.
摘要翻译：本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路，驱动器，使得每个单元格排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度为第二电平移位电路和预驱动器对应于低侧晶体管的单元宽度。

7. 发明申请

US20090302347A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090302347A1
公开(公告)日：2009-12-10
申请号：US11919504
申请日：2006-09-29
申请人： Hiroki Matsunaga , Masahiko Sasada , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Hiroki Matsunaga , Masahiko Sasada , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： H01L27/04 , H01L29/861
CPC分类号： H01L27/0207 , G09G3/296 , G09G2310/0289 , G09G2330/04 , H01L24/05 , H01L27/0251 , H01L27/0629 , H01L27/11803 , H01L2224/05554 , H01L2924/01004 , H01L2924/13055 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.
摘要翻译：半导体集成电路包括多个电路单元，每个电路单元包括半导体芯片上的焊盘。每个电路单元包括高侧晶体管，电平移位电路，低侧晶体管，预驱动器和焊盘。高侧晶体管和低侧晶体管被布置成彼此面对，垫间插入其间。

8. 发明授权

US5657098A Control circuit for use with a cut-off adjusting circuit and a drive adjusting circuit 失效
标题翻译：用于切断调节电路和驱动调节电路的控制电路
公开(公告)号：US5657098A
公开(公告)日：1997-08-12
申请号：US510519
申请日：1995-08-02
申请人： Hiroshi Ando , Hiroki Kinugawa , Masahiko Sasada
发明人： Hiroshi Ando , Hiroki Kinugawa , Masahiko Sasada
IPC分类号： H04N9/73 , H04N9/72 , H04N9/68
CPC分类号： H04N9/73
摘要： Control circuits for the cut-off and drive control of video equipment. A first control device includes a cut-off control circuit and drive control circuit for use in conventional modes. A second control device includes a cut-off control circuit for mode switching and a drive control circuit for mode switching, independent of the first control device. The cut-off and drive adjustments made for every mode switching operation are unnecessary, and the mode switching based on off set data is possible.
摘要翻译：用于视频设备的切断和驱动控制的控制电路。第一控制装置包括用于常规模式的截止控制电路和驱动控制电路。第二控制装置包括用于模式切换的截止控制电路和用于模式切换的驱动控制电路，与第一控制装置无关。对于每个模式切换操作进行的切断和驱动调节是不必要的，并且基于关闭设定数据的模式切换是可能的。

9. 发明授权

US5699127A Automatic brightness limiter automatic control circuit, contrast limiter control circuit, luminance/color difference signal processor and video display apparatus 失效
标题翻译：自动亮度限制器控制电路，自动对比度限制器控制电路，亮度/色差信号处理器和视频显示设备
公开(公告)号：US5699127A
公开(公告)日：1997-12-16
申请号：US519076
申请日：1995-08-24
申请人： Hiroshi Ando , Hiroki Kinugawa , Masahiko Sasada , Minoru Miyata
发明人： Hiroshi Ando , Hiroki Kinugawa , Masahiko Sasada , Minoru Miyata
IPC分类号： H04N5/57 , H04N5/59
CPC分类号： H04N5/68 , H04N5/57 , H04N7/0122
摘要： The object of the present invention is to easily compensate automatic brightness limiting performance and automatic contrast limiting performance even if a picture is displayed with a different aspect ratio and to prevent deterioration of picture quality such as gradation and sharpness. A picture display apparatus includes (1) an automatic brightness limiter (ABL) circuit including a comparison circuit for varying an EHT compensation starting point, an ABL gain control circuit for varying a slope of the EHT characteristic versus the APL, an ABL comparison voltage generator, a DAC for adjusting an ABL compensation starting point and a DAC for adjusting an ABL gain and (2) an automatic contrast limiter (ACL) circuit including another comparison circuit for varying an EHT compensation starting point, an ACL gain control circuit for varying a slope of the EHT characteristic versus the APL, an ACL comparison voltage generator, a DAC for adjusting an ACL compensation starting point and a DAC for adjusting an ACL gain.
摘要翻译：本发明的目的是即使以不同的纵横比显示图像并且防止诸如灰度和锐度的图像质量的劣化，也容易地补偿自动亮度限制性能和自动对比度限制性能。图像显示装置包括（1）包括用于改变EHT补偿起始点的比较电路的自动亮度限制器（ABL）电路，用于改变EHT特性对APL的斜率的ABL增益控制电路，ABL比较电压发生器，用于调整ABL补偿起始点的DAC和用于调整ABL增益的DAC，和（2）包括用于改变EHT补偿起始点的另一个比较电路的自动对比度限制器（ACL）电路，用于改变ABL增益的ACL增益控制电路 EHT特性与APL的斜率，ACL比较电压发生器，用于调整ACL补偿起始点的DAC和用于调整ACL增益的DAC。

10. 发明授权

US07030936B2 Pedestal level control circuit and method for controlling pedestal level 失效
公开(公告)号：US07030936B2
公开(公告)日：2006-04-18
申请号：US10184952
申请日：2002-07-01
申请人： Masahiko Sasada
发明人： Masahiko Sasada
IPC分类号： H04N5/16 , H04N5/18 , H04N5/57
CPC分类号： H04N5/57 , H04N5/16 , H04N5/44 , H04N9/73 , H04N21/426 , H04N21/4318
摘要： In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.

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