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1. 发明申请

US20050193156A1 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US20050193156A1
公开(公告)日：2005-09-01
申请号：US11037092
申请日：2005-01-19
申请人： Masafumi Inoue , Takanaga Yamazaki , Takeshi Kataoka , Hideo Kubota , Satoshi Tanaka , Hirokazu Komori , Takahiro Gotoh
发明人： Masafumi Inoue , Takanaga Yamazaki , Takeshi Kataoka , Hideo Kubota , Satoshi Tanaka , Hirokazu Komori , Takahiro Gotoh
IPC分类号： G06F13/24 , G06F9/00 , G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.
摘要翻译：本发明提供一种能够执行中断异常处理程序的数据处理系统，如果请求事件发生多次，则能够执行相同中断异常处理例程的请求事件发生次数的次数多次。当产生软件中断的软件处理或产生硬件中断的硬件事件发生时，软件中断计数器或用于保持中断请求生成事件发生次数的硬件中断计数器递增计数，当一个 CPU执行删除中断请求的处理。如果软件中断计数器的值和硬件中断计数器的值不为零，则向CPU发出软件中断请求信号和硬件中断请求信号。

2. 发明授权

US07464210B2 Data processing system having a data transfer unit for converting an integer into a floating-point number when tranferring data from a peripheral circuit to a memory 失效
标题翻译：数据处理系统具有数据传送单元，用于在将数据从外围电路传送到存储器时将整数转换为浮点数
公开(公告)号：US07464210B2
公开(公告)日：2008-12-09
申请号：US11037092
申请日：2005-01-19
申请人： Masafumi Inoue , Takanaga Yamazaki , Takeshi Kataoka , Hideo Kubota , Satoshi Tanaka , Hirokazu Komori , Takahiro Gotoh
发明人： Masafumi Inoue , Takanaga Yamazaki , Takeshi Kataoka , Hideo Kubota , Satoshi Tanaka , Hirokazu Komori , Takahiro Gotoh
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.
摘要翻译：本发明提供一种能够执行中断异常处理程序的数据处理系统，如果请求事件发生多次，则能够执行相同中断异常处理例程的请求事件发生次数的次数多次。当产生软件中断的软件处理或产生硬件中断的硬件事件发生时，软件中断计数器或用于保持中断请求生成事件发生次数的硬件中断计数器递增计数，当一个 CPU执行删除中断请求的处理。如果软件中断计数器的值和硬件中断计数器的值不为零，则向CPU发出软件中断请求信号和硬件中断请求信号。

3. 发明授权

US07020764B2 Semiconductor processing device 有权
标题翻译：半导体处理装置
公开(公告)号：US07020764B2
公开(公告)日：2006-03-28
申请号：US10621330
申请日：2003-07-18
申请人： Hideo Kubota , Takanaga Yamazaki
发明人： Hideo Kubota , Takanaga Yamazaki
IPC分类号： H03K19/173 , G06F15/76
CPC分类号： G06F15/7867 , G06F15/7814 , G11C7/20
摘要： A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit in the device in a very short time. The LSI includes a CPU, a flash memory which is a nonvolatile memory, a programmable logic which is a SRAM-type field programmable gate array, and a configuration circuit which implements the logic circuit configuration operation. At the event of power-on reset, logic building data stored in the flash memory is transferred to the programmable logic to establish a logic circuit in it under control of the configuration circuit, so that the logic circuit built in the programmable logic can be used immediately after the power-on reset of the device.
摘要翻译：有用的半导体处理设备（LSI）能够在用户系统开发的最后阶段实现信号的精确设置，并且使用户能够在非常短的时间内在设备中构建逻辑电路。 LSI包括CPU，作为非易失性存储器的闪存，作为SRAM型现场可编程门阵列的可编程逻辑，以及实现逻辑电路配置操作的配置电路。在上电复位的情况下，存储在闪速存储器中的逻辑建立数据被传送到可编程逻辑以在配置电路的控制下建立逻辑电路，从而可以使用内置在可编程逻辑中的逻辑电路在设备上电复位后立即进行。

4. 发明授权

US3969311A Fiber reinforced polyester resin having a low surface profile 失效
标题翻译：具有低表面轮廓的纤维增强聚酯树脂
公开(公告)号：US3969311A
公开(公告)日：1976-07-13
申请号：US564713
申请日：1975-04-03
申请人： Hideo Kubota
发明人： Hideo Kubota
IPC分类号： C08F299/04 , C08K13/04 , C08L67/06
CPC分类号： C08F299/0478 , C08K13/04 , C08K3/26 , C08K3/40
摘要： In accordance with a preferred embodiment of this invention, a fiber reinforced polyester article having a low surface profile is produced from a material which may be used either as a bulk molding or as a sheet molding compound. Preferably, this composition is produced from a formulation comprising about equal proportions of (1) an unsaturated polyester condensation product dissolved in (2) a copolymerizable reactive diluent solution of from proportionally 11/2 to 2 parts by weight of tertiary butyl styrene per each part of styrene. This formulation will of course also contain a filler such as a particulate calcium carbonate and reinforcing glass fibers. It is the specific combination of styrene and tertiary butyl styrene which promotes the low profile surface in the final molded article.
摘要翻译：根据本发明的一个优选实施例，具有低表面轮廓的纤维增强聚酯制品由可以作为大块模塑或片状模塑料使用的材料制成。优选地，该组合物由包含大约相等比例的（1）溶解在（2）可共聚的反应性稀释液中的不饱和聚酯缩合产物的制剂制备，所述不饱和聚酯缩合产物每个部分按比例为11/2至2重量份的叔丁基苯乙烯的苯乙烯。该制剂当然也将含有填料如碳酸钙颗粒和增强玻璃纤维。苯乙烯和叔丁基苯乙烯的特殊组合促进了最终成型制品中的低轮廓表面。

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