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1. 发明授权

US07663179B2 Semiconductor device with rewritable nonvolatile memory cell 有权
标题翻译：具有可重写非易失性存储单元的半导体器件
公开(公告)号：US07663179B2
公开(公告)日：2010-02-16
申请号：US11443252
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , H01L27/115
摘要： A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor. The sidewall spacers of the first field effect transistor include a first silicon oxide film, a first silicon nitride film over the first silicon oxide film and a second silicon oxide film over the first silicon nitride film.
摘要翻译：一种半导体器件，具有可重写非易失性存储单元，其包括用于存储的第一场效应晶体管，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，所述晶体管包括形成在半导体衬底上的栅极绝缘膜，在栅极绝缘膜上方的栅电极和相应栅电极的侧壁上的侧壁间隔物。第一场效应晶体管的侧壁间隔物与至少第二场效应晶体管的侧壁间隔物不同。此外，第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的栅极绝缘膜，第三场效应晶体管的栅电极的长度与第一场效应晶体管或第二场效应晶体管的长度不同效应晶体管。第一场效应晶体管的侧壁间隔物包括第一氧化硅膜，第一氧化硅膜上的第一氮化硅膜和位于第一氮化硅膜上的第二氧化硅膜。

2. 发明申请

US20060228860A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060228860A1
公开(公告)日：2006-10-12
申请号：US11443257
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0466 , H01L27/105 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.
摘要翻译：一种半导体器件的制造方法，用于形成包括用于存储器的第一场效应晶体管的可重写非易失性存储单元，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，包括在半导体衬底上形成栅极绝缘膜栅极绝缘膜上的栅电极和与第一至第三场效应晶体管中的每一个相关联的栅电极的侧壁上的侧壁隔离物。至少第一场效应晶体管的侧壁间隔物具有与至少第二场效应晶体管不同的宽度，第三场效应晶体管的栅电极具有与至少第一场效应晶体管不同的长度，存储器和第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的厚度。

3. 发明授权

US07118972B2 Method of manufacture of a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07118972B2
公开(公告)日：2006-10-10
申请号：US10833118
申请日：2004-04-28
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L21/8234
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacture of a semiconductor device uses simplified steps while improving the electrical properties of each element in the semiconductor device. Over a semiconductor substrate, having a memory gate electrode, control gate electrode and gate electrode formed thereover, a silicon oxide film, a silicon nitride film and a silicon oxide film are formed successively. The silicon oxide film formed over the gate electrode is then removed by wet etching. The silicon oxide film, silicon nitride film and silicon oxide film formed over the semiconductor substrate are removed successively by anisotropic dry etching, whereby respective sidewall spacers having a relatively large width and a relatively small width are formed.
摘要翻译：半导体器件的制造方法使用简化的步骤，同时改善半导体器件中每个元件的电性能。在其上形成有存储栅电极，控制栅电极和栅电极的半导体衬底上，依次形成氧化硅膜，氮化硅膜和氧化硅膜。然后通过湿蚀刻除去在栅电极上形成的氧化硅膜。形成在半导体衬底上形成的氧化硅膜，氮化硅膜和氧化硅膜通过各向异性干蚀刻连续地去除，从而形成具有相对较大宽度和相对较小宽度的各个侧壁间隔物。

4. 发明授权

US07348245B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07348245B2
公开(公告)日：2008-03-25
申请号：US11443257
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L21/8234
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0466 , H01L27/105 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.
摘要翻译：一种半导体器件的制造方法，用于形成包括用于存储器的第一场效应晶体管的可重写非易失性存储单元，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，包括在半导体衬底上形成栅极绝缘膜栅极绝缘膜上的栅电极和与第一至第三场效应晶体管中的每一个相关联的栅电极的侧壁上的侧壁隔离物。至少第一场效应晶体管的侧壁间隔物具有与至少第二场效应晶体管不同的宽度，第三场效应晶体管的栅电极具有与至少第一场效应晶体管不同的长度，存储器和第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的厚度。

5. 发明申请

US20060214256A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214256A1
公开(公告)日：2006-09-28
申请号：US11443252
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115
摘要： A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor. The sidewall spacers of the first field effect transistor include a first silicon oxide film, a first silicon nitride film over the first silicon oxide film and a second silicon oxide film over the first silicon nitride film.
摘要翻译：一种半导体器件，具有可重写非易失性存储单元，其包括用于存储的第一场效应晶体管，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，所述晶体管包括形成在半导体衬底上的栅极绝缘膜，在栅极绝缘膜上方的栅电极和相应栅电极的侧壁上的侧壁间隔物。第一场效应晶体管的侧壁间隔物与至少第二场效应晶体管的侧壁间隔物不同。此外，第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的栅极绝缘膜，第三场效应晶体管的栅电极的长度与第一场效应晶体管或第二场效应晶体管的长度不同效应晶体管。第一场效应晶体管的侧壁间隔物包括第一氧化硅膜，第一氧化硅膜上的第一氮化硅膜和位于第一氮化硅膜上的第二氧化硅膜。

6. 发明授权

US06423584B1 method for forming capacitors and field effect transistors in a semiconductor integrated circuit device 有权
公开(公告)号：US06423584B1
公开(公告)日：2002-07-23
申请号：US09811598
申请日：2001-03-20
申请人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
发明人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
IPC分类号： H01L2100
摘要： A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.

7. 发明授权

US06803644B2 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06803644B2
公开(公告)日：2004-10-12
申请号：US09768471
申请日：2001-01-25
申请人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
发明人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
IPC分类号： H01L29866
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11546 , Y10S438/983
摘要： A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.
摘要翻译：用于将齐纳二极管（D1，D2）和导线21和22的n +型半导体区域20彼此连接的多个连接孔24不布置在n +型半导体区域20的中心，在p +型半导体区域6和n +型半导体区域20形成结的区域中，配置在比结合深度的中心深的周边的区域。此外，这些连接孔24彼此间隔开，使得相邻的连接孔24之间的间距大于电路的连接孔之间的最小间距，从而当各个连接孔24为通过干蚀刻形成。

8. 发明授权

US06420754B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06420754B2
公开(公告)日：2002-07-16
申请号：US09791832
申请日：2001-02-26
申请人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
发明人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
IPC分类号： H01L29792
CPC分类号： H01L27/11521 , G11C7/18 , G11C16/0416 , H01L27/115 , H01L29/42324
摘要： A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.
摘要翻译：用作外围电路的场效应晶体管的栅电极由与非易失性存储单元的双电平栅电极结构相同的栅电极结构构成。用于连接用作外围电路的第一场效应晶体管的栅电极的两层的孔设置在与栅电极的平面内的有源区二维重叠的位置处，并且用于连接两个用作外围电路的第二场效应晶体管的栅电极的层设置在与栅电极的平面内的隔离区域二维重叠的位置处。第一场效应晶体管的栅极长度比第二场效应晶体管的栅极长度长，第一场效应晶体管的栅极宽度比第二场效应晶体管的栅极宽。

9. 发明授权

US08517280B2 IC card 失效
标题翻译： IC卡
公开(公告)号：US08517280B2
公开(公告)日：2013-08-27
申请号：US12884550
申请日：2010-09-17
申请人： Fukuo Owada
发明人： Fukuo Owada
IPC分类号： G06K19/06
CPC分类号： H01Q7/00 , G06K19/07784 , H01Q1/2225 , H01Q21/29
摘要： A contactless IC card which ensures the reliability of an IC chip mounted therein. Even if the distance between the contactless IC card and a reader/writer is too short, the card prevents an excessive voltage from being applied to the IC chip so that breakdown or reliability deterioration of the circuitry of the IC chip does not occur. The body of the contactless IC card has two interconnection substrates stacked between two external sheets. A first antenna coil formed on one interconnection substrate and a second antenna coil formed on the other interconnection substrate are opposite in winding direction. The number of turns of the second antenna coil is larger than that of the first antenna coil. Therefore, when the IC card comes close to the reader/writer, the voltage between two terminals of the IC chip is always smaller than the voltage induced in the second antenna coil.
摘要翻译：一种确保安装在其中的IC芯片的可靠性的非接触IC卡。即使非接触式IC卡与读写器之间的距离太短，卡也防止过大的电压施加到IC芯片上，从而不会发生IC芯片的电路的故障或可靠性恶化。非接触式IC卡的主体具有堆叠在两个外部片之间的两个互连基板。形成在一个互连基板上的第一天线线圈和形成在另一个互连基板上的第二天线线圈在卷绕方向上相反。第二天线线圈的匝数大于第一天线线圈的匝数。因此，当IC卡靠近读取器/写入器时，IC芯片的两个端子之间的电压总是小于在第二天线线圈中感应的电压。

10. 发明授权

US07064090B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07064090B2
公开(公告)日：2006-06-20
申请号：US10942860
申请日：2004-09-17
申请人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
发明人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
IPC分类号： H01L21/00
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11546 , Y10S438/983
摘要： A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.
摘要翻译：一种用于齐纳二极管的制造技术，其包括在半导体衬底的初级面的诸如阱区域的区域中形成第一半导体区域，然后在其上形成相反导电类型的第二半导体区域。第二半导体区域覆盖大于下面的第一半导体区域的面积。该方法还要求在衬底的主面上形成绝缘膜，然后在绝缘膜中形成连接孔，以暴露第二半导体区域的上部，该第二半导体区域的上部位于由第一和第二半导体区域。接着在绝缘膜的上部形成通过分布布置的多个连接孔在电线和第二半导体区域之间形成电连接的导线。

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