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1. 发明授权

US5187556A CMOS master slice 失效
标题翻译： CMOS MASTER SLICE
公开(公告)号：US5187556A
公开(公告)日：1993-02-16
申请号：US743089
申请日：1991-08-09
申请人： Masaaki Nariishi , Noboru Yamakawa , Osamu Ohba , Naoyasu Seki
发明人： Masaaki Nariishi , Noboru Yamakawa , Osamu Ohba , Naoyasu Seki
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L2027/11838
摘要： A CMOS master slice having a plurality of regularly arranged basic cells improves an integration efficiency by optimizing size and arrangement of MOS transistors in the basic cells. Each of the basic cells comprises a first pair of transistors having gates thereof arranged to parallelly face each other, and a second pair of transistors having gate electrodes shorter in gate width than that of the first pair of transistors and parallel to the gate electrodes of the first pair of transistors. In adjacent basic cells, the gate electrodes of adjacent second transistors are substantially on a line so that a wasteful space is eliminated.

2. 发明授权

US5444275A Radial gate array cell 失效
标题翻译：径向栅阵列单元
公开(公告)号：US5444275A
公开(公告)日：1995-08-22
申请号：US058665
申请日：1993-05-10
申请人： Masahiro Kugishima , Hiroyuki Sato , Masaaki Nariishi , Noboru Yamakawa , Takahiro Yamamoto
发明人： Masahiro Kugishima , Hiroyuki Sato , Masaaki Nariishi , Noboru Yamakawa , Takahiro Yamamoto
IPC分类号： H01L27/118
CPC分类号： H01L27/11807
摘要： Gate width directions of transistors are taken in circumferential directions surrounding a certain point as a center. Or transistors are constructed by a plurality of straight lines extending in radial directions of the certain point and intersecting each other at the same angle. Hereby, basic cells can be assembled on a master slice symmetrically in plural directions. There are arranged in a mutual adjacent relation in which channel layers located under one opposing gate electrodes are formed into P channels and channel layers located under the other opposing gate electrodes are formed into N channels. Otherwise, there are arranged alternately with respect to P channels and N channels in an adjacent relation basic cells in which all channel layers located under all gate electrodes in the same basic cell are formed by any type of the P channel and the N channel.
摘要翻译：晶体管的栅极宽度方向以围绕某一点为中心的圆周方向取。或者，晶体管由在该特定点的径向方向上延伸并以相同的角度彼此相交的多条直线构成。因此，基本单元可以在多个方向上对称地组装在主切片上。布置在相互相邻的关系中，其中位于一个相对的栅电极下方的沟道层形成为P沟道，并且位于其他相对的栅电极下方的沟道层形成为N沟道。否则，相对于相邻基站中的P信道和N个信道交替布置，其中位于同一基站中的所有栅电极下方的所有信道层由任何类型的P信道和N信道形成。

3. 发明授权

US5936423A Semiconductor IC with an output circuit power supply used as a signal input/output terminal 失效
标题翻译：具有输出电路电源的半导体IC用作信号输入/输出端子
公开(公告)号：US5936423A
公开(公告)日：1999-08-10
申请号：US766341
申请日：1996-12-16
申请人： Yuji Sakuma , Masaaki Nariishi
发明人： Yuji Sakuma , Masaaki Nariishi
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , H03K19/173 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/1732
摘要： An object of the present invention is to decrease the number of terminals of a semiconductor integrated circuit by utilizing one terminal for a plurality of purposes, and reduce the cost of it, suppressing the performance degradation of the semiconductor integrated circuit. The present invention can be adapted to a semiconductor integrated circuit in which at least one of power supply terminals or ground terminals connected on a power supply path of an output circuit of the semiconductor integrated circuit is installed independently of a power supply path of an internal circuit. In a normal operation mode in which a test mode input terminal .PHI. is low, power is supplied to an output circuit 5 through an output circuit power supply/testing signal input terminal OVDD/TIN. In a test mode in which the test mode input terminal .PHI. is high, the output circuit power supply/testing signal input terminal OVDD/TIN is used to input a signal from outside of the integrated circuit or to output a signal sent from an internal circuit 3. In the test mode, a switching device SW1 on a final stage forming the output circuit is turned OFF by a cutoff circuit, and the terminal OVDD/TIN is disconnected from an output terminal U and can therefore be used as an input terminal for the testing signal.
摘要翻译：本发明的目的是通过利用多个目的的一个端子来减少半导体集成电路的端子数量，并降低其成本，抑制半导体集成电路的性能劣化。本发明可以适用于半导体集成电路，其中连接在半导体集成电路的输出电路的电源路径上的电源端子或接地端子中的至少一个独立于内部电路的电源路径而被安装。在测试模式输入端子PHI为低的正常工作模式下，通过输出电路供电/测试信号输入端子OVDD / TIN向输出电路5供电。在测试模式输入端子PHI为高电平的测试模式下，输出电路供电/测试信号输入端OVDD / TIN用于从集成电路外部输入信号，或输出从内部电路发送的信号在测试模式中，形成输出电路的最终级的开关器件SW1由截止电路断开，并且端子OVDD / TIN与输出端子U断开，因此可用作输入端子测试信号。

4. 发明授权

US5581097A Method of fabricating semiconductor device using shared contact hole masks and semiconductor device using same 失效
标题翻译：使用共用接触孔掩模制造半导体器件的方法和使用其的半导体器件
公开(公告)号：US5581097A
公开(公告)日：1996-12-03
申请号：US321736
申请日：1994-10-12
申请人： Masaaki Nariishi
发明人： Masaaki Nariishi
IPC分类号： H01L27/118 , H01L27/10 , H01L23/48 , H01L23/52
CPC分类号： H01L27/11807
摘要： A semi-custom semiconductor device adapted for a master slice approach includes basic cells arranged in an array, wherein the cells are configured such that connection hole placeable positions are at lattice points of a grid which is spaced a predetermined distance from a custom wiring grid having a uniform predetermined lattice spacing. The semiconductor device is prepared by forming basic cells in a silicon wafer as an array, forming a first interlayer insulating film thereon, perforating contact holes at all contact hole placeable positions aligned with lattice points of a grid spaced a predetermined distance from a customizing wiring grid through a contact hole sharing mask, forming a first metal layer thereon, thereby providing a master wafer, etching the master wafer through a custom mask to form a first metal wiring layer on the custom wiring grid and between it and the contact hole, forming a second interlayer insulating film-thereon, perforating via holes at via hole placeable positions aligned with lattice points of a grid spaced a predetermined distance from the customizing wiring grid, forming a second metal layer thereon, and etching the second metal layer to form a second metal wiring layer. The invention facilitates designing, reduces the development cost, and advances the delivery date of a semi-custom semiconductor device.
摘要翻译：适用于主切片方法的半定制半导体器件包括以阵列布置的基本单元，其中单元被配置为使得连接孔可放置位置处于与具有预定距离的定影布线栅格隔开预定距离的栅格的格点处，均匀的预定晶格间距。半导体器件通过在硅晶片中形成基底单元作为阵列来制备，在其上形成第一层间绝缘膜，在与定制布线栅格隔开预定距离的网格的格子点对齐的所有接触孔可放置位置处穿孔接触孔通过接触孔共享掩模，在其上形成第一金属层，由此提供母晶片，通过定制掩模蚀刻母晶片，以在定制布线栅格上并在其与接触孔之间形成第一金属布线层，形成第二层间绝缘膜，在通孔可放置位置上穿过通孔，与与定制布线栅格隔开预定距离的网格的格点对齐，在其上形成第二金属层，并蚀刻第二金属层以形成第二金属接线层。本发明便于设计，降低开发成本，并且提高半定制半导体器件的交付日期。

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