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1. 发明授权

US08396333B2 Image pickup apparatus, solid-state imaging device, and image generating method 有权
标题翻译：图像拾取装置，固态成像装置和图像生成方法
公开(公告)号：US08396333B2
公开(公告)日：2013-03-12
申请号：US13181090
申请日：2011-07-12
申请人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
发明人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
IPC分类号： G06K7/00 , G09G5/00
CPC分类号： H04N5/232 , H04N5/23245
摘要： In an image pickup apparatus of the present invention, a CCD 11 in which a plurality of pixels are arranged in a two-dimensional array, thereof the number of effective horizontal pixels is H and the number of effective vertical pixels is V; a aspect switching operator 18 that sets one of a plurality of aspect modes including a first aspect mode and a second aspect mode; an image processor 141 that generates first image data for recording in the first aspect mode, and generates second image data for recording in the second aspect mode, wherein the first image data for recording is generated using image data that is generated with pixels being H1 horizontal pixels by V1 vertical pixels included in the pixels on the CCD 11 or image data that is obtained by subjecting said image data to predetermined processing, the second image data for recording is generated using image data that is generated with pixels being H2 horizontal pixels by V2 vertical pixels included in the pixels on the solid-state imaging device or image data that is obtained by subjecting said image data to predetermined processing, and the first image data for recording and the second image data for recording satisfy the following relationships: H2
摘要翻译：在本发明的图像拾取装置中，其中多个像素排列成二维阵列的CCD11，有效水平像素数为H，有效垂直像素数为V; 设置包括第一方面模式和第二方面模式的多个方面模式之一的方面切换操作器18; 图像处理器141，其生成用于在第一方面模式中记录的第一图像数据，并且生成用于在第二方面模式中记录的第二图像数据，其中用于记录的第一图像数据使用以水平为H1的像素生成的图像数据生成包含在CCD 11上的像素中的V1垂直像素的像素或通过对所述图像数据进行预定处理而获得的图像数据，使用以H 2水平像素的像素乘以V2生成的图像数据生成用于记录的第二图像数据包括在固态成像装置中的像素中的垂直像素或通过对所述图像数据进行预定处理而获得的图像数据，并且用于记录的第一图像数据和用于记录的第二图像数据满足以下关系：H2

2. 发明授权

US08005320B2 Image pickup apparatus, solid-state imaging device, and image generating method 有权
标题翻译：图像拾取装置，固态成像装置和图像生成方法
公开(公告)号：US08005320B2
公开(公告)日：2011-08-23
申请号：US12633373
申请日：2009-12-08
申请人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
发明人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
IPC分类号： G06K7/00 , H04N5/222 , H04N7/01 , H04N5/335
CPC分类号： H04N5/232 , H04N5/23245
摘要： In an image pickup apparatus of the present invention, a CCD 11 in which a plurality of pixels are arranged in a two-dimensional array, thereof the number of effective horizontal pixels is H and the number of effective vertical pixels is V; a aspect switching operator 18 that sets one of a plurality of aspect modes including a first aspect mode and a second aspect mode; an image processor 141 that generates first image data for recording in the first aspect mode, and generates second image data for recording in the second aspect mode, wherein the first image data for recording is generated using image data that is generated with pixels being H1 horizontal pixels by V1 vertical pixels included in the pixels on the CCD 11 or image data that is obtained by subjecting said image data to predetermined processing, the second image data for recording is generated using image data that is generated with pixels being H2 horizontal pixels by V2 vertical pixels included in the pixels on the solid-state imaging device or image data that is obtained by subjecting said image data to predetermined processing, and the first image data for recording and the second image data for recording satisfy the following relationships: H2
摘要翻译：在本发明的图像拾取装置中，其中多个像素排列成二维阵列的CCD11，有效水平像素数为H，有效垂直像素数为V; 设置包括第一方面模式和第二方面模式的多个方面模式之一的方面切换操作器18; 图像处理器141，其生成用于在第一方面模式中记录的第一图像数据，并且生成用于在第二方面模式中记录的第二图像数据，其中用于记录的第一图像数据使用以水平为H1的像素生成的图像数据生成包含在CCD 11上的像素中的V1垂直像素的像素或通过对所述图像数据进行预定处理而获得的图像数据，使用以H 2水平像素的像素乘以V2生成的图像数据生成用于记录的第二图像数据包括在固态成像装置中的像素中的垂直像素或通过对所述图像数据进行预定处理而获得的图像数据，并且用于记录的第一图像数据和用于记录的第二图像数据满足以下关系：H2

3. 发明授权

US07653266B2 Image pickup apparatus, solid-state imaging device, and image generating method 有权
标题翻译：图像拾取装置，固态成像装置和图像生成方法
公开(公告)号：US07653266B2
公开(公告)日：2010-01-26
申请号：US11531892
申请日：2006-09-14
申请人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
发明人： Masaaki Nakayama , Shinobu Fusa , Ichiro Kitao , Kenji Maeda
IPC分类号： G06K7/00 , H04N5/335 , H04N3/14
CPC分类号： H04N5/232 , H04N5/23245
摘要： In an image pickup apparatus of the present invention, a CCD 11 in which a plurality of pixels are arranged in a two-dimensional array, thereof the number of effective horizontal pixels is H and the number of effective vertical pixels is V; a aspect switching operator 18 that sets one of a plurality of aspect modes including a first aspect mode and a second aspect mode; an image processor 141 that generates first image data for recording in the first aspect mode, and generates second image data for recording in the second aspect mode, wherein the first image data for recording is generated using image data that is generated with pixels being H1 horizontal pixels by V1 vertical pixels included in the pixels on the CCD 11 or image data that is obtained by subjecting said image data to predetermined processing, the second image data for recording is generated using image data that is generated with pixels being H2 horizontal pixels by V2 vertical pixels included in the pixels on the solid-state imaging device or image data that is obtained by subjecting said image data to predetermined processing, and the first image data for recording and the second image data for recording satisfy the following relationships: H2
摘要翻译：在本发明的图像拾取装置中，其中多个像素排列成二维阵列的CCD11，有效水平像素数为H，有效垂直像素数为V; 设置包括第一方面模式和第二方面模式的多个方面模式之一的方面切换操作器18; 图像处理器141，其生成用于在第一方面模式中记录的第一图像数据，并且生成用于在第二方面模式中记录的第二图像数据，其中用于记录的第一图像数据使用以水平为H1的像素生成的图像数据生成包含在CCD 11上的像素中的V1垂直像素的像素或通过对所述图像数据进行预定处理而获得的图像数据，使用以H 2水平像素的像素乘以V2生成的图像数据生成用于记录的第二图像数据包括在固态成像装置中的像素中的垂直像素或通过对所述图像数据进行预定处理而获得的图像数据，并且用于记录的第一图像数据和用于记录的第二图像数据满足以下关系：H2

4. 发明授权

US6133756A Output buffer control circuit 有权
标题翻译：输出缓冲器控制电路
公开(公告)号：US6133756A
公开(公告)日：2000-10-17
申请号：US266888
申请日：1999-03-12
申请人： Ichiro Kitao
发明人： Ichiro Kitao
IPC分类号： H03K17/16 , H03K3/356 , H03K17/687 , H03K17/693 , H03K19/0175
CPC分类号： H03K17/693 , H03K3/356104
摘要： An output buffer control circuit in which an amplitude of a gate input of a MOS transistor for the output's sake is variable by virtue of a program or a mask option, thus there is no electromagnetic interference caused by excessive output current and unnecessary current consumption, is suitable in use for universal integrated circuit. A gate voltage selector circuit selects one out of three voltages (V.sub.DD +.alpha.), V.sub.DD, and (V.sub.DD -.beta.) in accordance with the combination of selection signals S.sub.1, S.sub.2, and S.sub.3. A level conversion circuit performs ON-OFF of a voltage V.sub.1 selected by the gate voltage selector circuit in accordance with a source output signal to be outputted to an outer section with the same cycle as the source output signal, thus communicating it as a gate input to an n-MOS transistor of an output buffer. It is equivalent to that it causes amplitude V.sub.DD of the source output signal to be performed level conversion toward the voltage V.sub.1 which the gate voltage selector circuit selects. It is capable of being obtained the optimum output current because the amplitude V.sub.1 undergoing the level conversion is variable by virtue of the selection signals S.sub.1, S.sub.2, and S.sub.3.
摘要翻译：一种输出缓冲器控制电路，其中通过程序或掩码选项，MOS晶体管的栅极输入的幅度可变，因此不会产生过大的输出电流和不必要的电流消耗引起的电磁干扰，适用于通用集成电路。栅极电压选择器电路根据选择信号S1，S2和S3的组合来选择三个电压（VDD +α），VDD和（VDD-β）中的一个。电平转换电路根据源输出信号，由栅极电压选择电路选择的电压V1进行ON-OFF，以与源极输出信号相同的周期输出到外部，从而将其作为栅极输入到输出缓冲器的n-MOS晶体管。相当于使源极输出信号的幅度VDD向栅极电压选择电路选择的电压V1进行电平转换。由于通过选择信号S1，S2和S3，进行电平转换的振幅V1是可变的，所以能够获得最佳的输出电流。

5. 发明授权

US06694452B1 Data processor and method of processing data 有权
标题翻译：数据处理器和数据处理方法
公开(公告)号：US06694452B1
公开(公告)日：2004-02-17
申请号：US09472037
申请日：1999-12-27
申请人： Ichiro Kitao
发明人： Ichiro Kitao
IPC分类号： G06F1100
CPC分类号： G06F21/56 , G06F1/24
摘要： A data processor includes a data memory for reading and writing data, a reset detector for detecting any factor of requirement for a reset operation and generating a reset signal. The data processor also includes a data processing unit connected to the data memory for controlling read and write operations of the data memory and also connected to the reset detector for receiving the reset signal from the reset detector to execute a reset operation of the data processor in accordance with the reset signal. The data processor further includes a non-volatile reset memory connected to the reset detector for storing history of outputting the reset signal from the reset detector.
摘要翻译：数据处理器包括用于读取和写入数据的数据存储器，用于检测复位操作的任何要求因素并产生复位信号的复位检测器。数据处理器还包括连接到数据存储器的数据处理单元，用于控制数据存储器的读和写操作，并且还连接到复位检测器，用于从复位检测器接收复位信号，以执行数据处理器的复位操作按照复位信号。数据处理器还包括连接到复位检测器的非易失性复位存储器，用于存储从复位检测器输出复位信号的历史。

6. 发明授权

US6081889A Method of resetting a system 失效
标题翻译：复位系统的方法
公开(公告)号：US6081889A
公开(公告)日：2000-06-27
申请号：US100817
申请日：1998-06-19
申请人： Ichiro Kitao
发明人： Ichiro Kitao
IPC分类号： G11C16/02 , G06F1/24 , G11C16/22
CPC分类号： G11C16/225 , G06F1/24
摘要： A method of resetting a system enables an EEPROM writing to be implemented to the end normally, and it is capable of avoiding runaway of the whole system, even if reset signal is received because of a power failure while the EEPROM is in the writing state. In the system which has a CPU, an EEPROM whole circuit, an oscillation circuit, and a reset control circuit, when a system reset occurs, the method includes detecting a writing operation of the EEPROM cell, in cases where the EEPROM cell is implementing the writing operation, holding the reset of the EEPROM cell until the writing operation of the EEPROM cell is terminated, thus implementing the reset of at least the CPU.
摘要翻译：复位系统的方法使得EEPROM写入能够正常地实现，即使在EEPROM处于写入状态时由于电源故障而接收到复位信号，也能够避免整个系统的失控。在具有CPU，EEPROM全电路，振荡电路和复位控制电路的系统中，当发生系统复位时，该方法包括检测EEPROM单元的写入操作，在EEPROM单元正在执行写入操作，保持EEPROM单元的复位，直到EEPROM单元的写入操作终止，从而实现至少CPU的复位。

7. 发明授权

US5712586A Semiconductor integrated system comprising an output voltage level-selecting circuit 失效
标题翻译：半导体集成系统包括输出电压电平选择电路
公开(公告)号：US5712586A
公开(公告)日：1998-01-27
申请号：US669181
申请日：1996-06-24
申请人： Ichiro Kitao
发明人： Ichiro Kitao
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K19/0175 , H03K5/00
CPC分类号： H03K19/017581
摘要： In a semiconductor integrated system comprising an internal circuit (6) for operating in an internal voltage having a low voltage level and for producing an output control signal and an output signal having the low voltage level, a voltage level-selecting circuit (23) selects one of high and low level output terminals in response to the output control signal to supply the output signal to the one of the high and low level output terminals. A voltage level shifter (7) shifts the output signal to produce a shifted output signal having a high voltage level which is higher than the low voltage level.
摘要翻译：在包括用于在具有低电压电平的内部电压中操作并用于产生输出控制信号和具有低电压电平的输出信号的内部电路（6）的半导体集成系统中，电压电平选择电路（23）选择响应于输出控制信号的高电平和低电平输出端之一，以将输出信号提供给高电平和低电平输出端中的一个。电压电平移位器（7）移位输出信号以产生具有高于低电压电平的高电压电平的移位输出信号。

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