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1. 发明申请

US20080099760A1 Picture element driving circuit of display panel and display device using the same 审中-公开
标题翻译：显示面板的图像元件驱动电路及使用其的显示装置
公开(公告)号：US20080099760A1
公开(公告)日：2008-05-01
申请号：US11976298
申请日：2007-10-23
申请人： Masaaki Fujimori , Takeo Shiba , Masahiko Ando , Masahiro Kawasaki , Tomihiro Hashizume
发明人： Masaaki Fujimori , Takeo Shiba , Masahiko Ando , Masahiro Kawasaki , Tomihiro Hashizume
IPC分类号： H01L51/05
CPC分类号： H01L27/3274 , H01L27/1292 , H01L27/283 , H01L51/0004
摘要： The present invention provides a picture element driving circuit of an active matrix display device, with a configuration of no through-holes, including two or more FETs. A display device of the present invention has a structure in which a first field-effect transistor and a second field-effect transistor are provided, insulation films of the first and second field-effect transistor are formed on the same layer, and semiconductors used as channels of the two field-effect transistors are formed on both surfaces of the insulation film, respectively. The display device has an electric circuit of a structure in which one of source/drain electrodes of the first field-effect transistor is used as a gate electrode of the second field-effect transistor.
摘要翻译：本发明提供一种有源矩阵显示装置的像素驱动电路，具有不包括两个或更多个FET的通孔的结构。本发明的显示装置具有其中设置有第一场效应晶体管和第二场效应晶体管的结构，第一和第二场效应晶体管的绝缘膜形成在同一层上，半导体用作两个场效应晶体管的沟道分别形成在绝缘膜的两个表面上。显示装置具有其中使用第一场效应晶体管的源极/漏极之一作为第二场效应晶体管的栅电极的结构的电路。

2. 发明授权

US07868323B2 Thin film transistor device, image display device and manufacturing method thereof 有权
标题翻译：薄膜晶体管器件，图像显示器件及其制造方法
公开(公告)号：US07868323B2
公开(公告)日：2011-01-11
申请号：US11953065
申请日：2007-12-09
申请人： Takeo Shiba , Masahiko Ando , Masahiro Kawasaki , Masaaki Fujimori
发明人： Takeo Shiba , Masahiko Ando , Masahiro Kawasaki , Masaaki Fujimori
IPC分类号： H01L35/24 , H01L51/00
CPC分类号： H01L27/286 , G02F1/13454 , G09G3/3225 , G09G2300/0426 , G09G2380/02 , H01L27/283 , H01L27/3274 , H01L27/3276 , H01L51/0545 , H01L2251/5338
摘要： In an image display device comprising a display part configured with a plurality of pixels and a peripheral integrated circuit which controls the display part, the display device is provided on a support substrate which has high durability for the impact and the bending, the pixel circuit is configured with an organic semiconductor TFT, the peripheral integrated circuit is configured with a low-temperature poly Si-TFT, this peripheral integrated circuit is provided on a support substrate of the display device being removed the support substrate when being manufactured, and the pixel circuit and the peripheral integrated circuit are connected with the same wire layer.
摘要翻译：在包括配置有多个像素的显示部分和控制显示部分的外围集成电路的图像显示装置中，显示装置设置在对冲击和弯曲具有高耐久性的支撑基板上，像素电路为配置有机半导体TFT的外围集成电路配置有低温多晶硅TFT，该外围集成电路设置在显示装置的支撑基板上，在制造时取出支撑基板，像素电路并且外围集成电路与相同的导线层连接。

3. 发明申请

US20080036698A1 Display 审中-公开
标题翻译：显示
公开(公告)号：US20080036698A1
公开(公告)日：2008-02-14
申请号：US11834736
申请日：2007-08-07
申请人： Masahiro Kawasaki , Masahiko Ando , Takeo Shiba , Shuji Imazeki , Masaaki Fujimori , Hideyuki Matsuoka
发明人： Masahiro Kawasaki , Masahiko Ando , Takeo Shiba , Shuji Imazeki , Masaaki Fujimori , Hideyuki Matsuoka
IPC分类号： G09G3/20
CPC分类号： G02F1/1368 , G09G3/20 , G09G2300/04 , H01L27/124 , H01L27/1292
摘要： A display arranged with, in a matrix way, signal lines for providing brightness information to each of pixels, and scanning lines for selecting, in a predetermined cycle, pixels to be provided with brightness information; intake of the brightness information to each of the pixels being executed by intake of signal voltage of the signal lines via thin-film transistors in each of said pixels, in selecting the scanning lines connected with each of the pixels; and having pixels of n-lines and m-rows, by which the brightness information taken into each of the pixels is retained by capacity thereof, even after the scanning lines connected with each of the pixels become a non-selection state, wherein each of the pixels of each line is provided with at least one semiconductor layer that is common between each of the pixels, and the semiconductor layer is formed in parallel to said signal lines.
摘要翻译：以矩阵方式布置用于向每个像素提供亮度信息的信号线和用于在预定周期中选择要提供亮度信息的像素的扫描线的显示器; 在选择与每个像素连接的扫描线时，通过每个所述像素中的薄膜晶体管吸收信号线的信号电压来执行每个像素的亮度信息的摄取; 并且即使在与每个像素连接的扫描线变为非选择状态之后，具有n行和m行的像素，由此通过其像素保留每个像素中的亮度信息，每行的像素设置有至少一个在每个像素之间共有的半导体层，并且半导体层与所述信号线并联形成。

4. 发明授权

US07872257B2 Organic thin film transistor array and method of manufacturing the same 有权
标题翻译：有机薄膜晶体管阵列及其制造方法
公开(公告)号：US07872257B2
公开(公告)日：2011-01-18
申请号：US12128993
申请日：2008-05-29
申请人： Tomihiro Hashizume , Yuji Suwa , Masaaki Fujimori , Tadashi Arai , Takeo Shiba
发明人： Tomihiro Hashizume , Yuji Suwa , Masaaki Fujimori , Tadashi Arai , Takeo Shiba
IPC分类号： H01L51/30 , H01L21/70
CPC分类号： H01L27/283 , H01L51/0003 , H01L51/0018 , H01L51/0021
摘要： An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.
摘要翻译：通过使用用于施加半导体和电极的界面和电极之间的费米能量的差异的大小的方程式，仅选择性地改变覆盖涂层而不改变TFT材料来实现n型TFT和p型TFT 半导体和绝缘体的界面。此时，为了构成规定的电路，作为p型TFT的源电极和漏电极，n型TFT的源电极和漏极全部分别连接，进行该处理并且通过使用扫描激光曝光装置等照射光而切断不必要的互连。

5. 发明申请

US20080315191A1 Organic Thin Film Transistor Array and Method of Manufacturing the Same 有权
标题翻译：有机薄膜晶体管阵列及其制造方法
公开(公告)号：US20080315191A1
公开(公告)日：2008-12-25
申请号：US12128993
申请日：2008-05-29
申请人： Tomihiro Hashizume , Yuji Suwa , Masaaki Fujimori , Tadashi Arai , Takeo Shiba
发明人： Tomihiro Hashizume , Yuji Suwa , Masaaki Fujimori , Tadashi Arai , Takeo Shiba
IPC分类号： H01L51/30 , H01L21/70
CPC分类号： H01L27/283 , H01L51/0003 , H01L51/0018 , H01L51/0021
摘要： An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.
摘要翻译：通过使用用于施加半导体和电极的界面和电极之间的费米能量的差异的大小的方程式，仅选择性地改变覆盖涂层而不改变TFT材料来实现n型TFT和p型TFT 半导体和绝缘体的界面。此时，为了构成规定的电路，作为p型TFT的源电极和漏电极，n型TFT的源电极和漏极全部分别连接，进行该处理并且通过使用扫描激光曝光装置等照射光而切断不必要的互连。

6. 发明申请

US20080087883A1 Organic Transistor Using Self-Assembled Monolayer 有权
标题翻译：有机晶体管使用自组装单层
公开(公告)号：US20080087883A1
公开(公告)日：2008-04-17
申请号：US11865769
申请日：2007-10-02
申请人： YUJI SUWA , Tomihiro Hashizume , Masahiko Ando , Takeo Shiba
发明人： YUJI SUWA , Tomihiro Hashizume , Masahiko Ando , Takeo Shiba
IPC分类号： H01L51/10 , H01L51/30
CPC分类号： H01L51/105 , H01L51/0545
摘要： Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also disclosed are a p-cannel FET, an n-channel FET, and a C-TFT which can be fabricated inexpensively. Specifically, a p-type region and an n-type region is inexpensively prepared on one substrate by arranging an organic semiconductor that is likely to work as a p-type semiconductor in a p-channel FET region and an n-channel FET region of a C-TFT; and arranging a self-assembled monolayer between an electrode and the organic semiconductor in the n-channel FET region, which self-assembled monolayer is capable of allowing the organic semiconductor to work as an n-type semiconductor.
摘要翻译：公开了一种在有机半导体的p型操作时廉价地降低电极和有机半导体之间的接触电阻的方法; 以及作为n型半导体廉价地操作有可能用作p型半导体的有机半导体的方法。此外，还公开了可以廉价制造的p型FET，n沟道FET和C-TFT。具体地说，在一个衬底上廉价地制备p型区域和n型区域，通过在p沟道FET区域和n沟道FET区域中配置可能作为p型半导体的有机半导体，一个C-TFT; 并且在n沟道FET区域中的电极和有机半导体之间布置自组装单层，该自组装单层能够使有机半导体作为n型半导体工作。

7. 发明授权

US07622734B2 Organic transistor using self-assembled monolayer 有权
标题翻译：有机晶体管采用自组装单层
公开(公告)号：US07622734B2
公开(公告)日：2009-11-24
申请号：US11865769
申请日：2007-10-02
申请人： Yuji Suwa , Tomihiro Hashizume , Masahiko Ando , Takeo Shiba
发明人： Yuji Suwa , Tomihiro Hashizume , Masahiko Ando , Takeo Shiba
IPC分类号： H01L51/00
CPC分类号： H01L51/105 , H01L51/0545
摘要： Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also disclosed are a p-cannel FET, an n-channel FET, and a C-TFT which can be fabricated inexpensively. Specifically, a p-type region and an n-type region is inexpensively prepared on one substrate by arranging an organic semiconductor that is likely to work as a p-type semiconductor in a p-channel FET region and an n-channel FET region of a C-TFT; and arranging a self-assembled monolayer between an electrode and the organic semiconductor in the n-channel FET region, which self-assembled monolayer is capable of allowing the organic semiconductor to work as an n-type semiconductor.
摘要翻译：公开了一种在有机半导体的p型操作时廉价地降低电极和有机半导体之间的接触电阻的方法; 以及作为n型半导体廉价地操作有可能用作p型半导体的有机半导体的方法。此外，还公开了可以廉价制造的p型FET，n沟道FET和C-TFT。具体地说，在一个衬底上廉价地制备p型区域和n型区域，通过在p沟道FET区域和n沟道FET区域中配置可能作为p型半导体的有机半导体，一个C-TFT; 并且在n沟道FET区域中的电极和有机半导体之间布置自组装单层，该自组装单层能够使有机半导体作为n型半导体工作。

8. 发明申请

US20090294852A1 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US20090294852A1
公开(公告)日：2009-12-03
申请号：US12385937
申请日：2009-04-24
申请人： Masahiro Kawasaki , Masaaki Fujimori , Takeo Shiba , Shuji Imazeki , Tadashi Arai
发明人： Masahiro Kawasaki , Masaaki Fujimori , Takeo Shiba , Shuji Imazeki , Tadashi Arai
IPC分类号： H01L29/786
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/055
摘要： A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.
摘要翻译：薄膜晶体管包括绝缘基板，源电极和漏电极，设置在绝缘基板的顶部上，分别与源极电连接的半导体层和漏极电极形成的栅极电介质膜至少在半导体层的顶部; 以及设置在栅极电介质膜的顶部上以与半导体层重叠的栅电极。此外，形成第一堤绝缘体以覆盖源电极，形成第二堤绝缘体以覆盖漏电极，并且半导体层，栅极电介质膜和栅极电极嵌入在第一银行绝缘子和第二银行绝缘子。

9. 发明授权

US08013327B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US08013327B2
公开(公告)日：2011-09-06
申请号：US12385937
申请日：2009-04-24
申请人： Masahiro Kawasaki , Masaaki Fujimori , Takeo Shiba , Shuji Imazeki , Tadashi Arai
发明人： Masahiro Kawasaki , Masaaki Fujimori , Takeo Shiba , Shuji Imazeki , Tadashi Arai
IPC分类号： H01L29/08 , H01L35/24 , H01L51/00 , H01L27/12 , H01L29/66
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/055
摘要： A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.
摘要翻译：薄膜晶体管包括绝缘基板，源电极和漏电极，设置在绝缘基板的顶部上，分别与源极电连接的半导体层和漏极电极形成的栅极电介质膜至少在半导体层的顶部; 以及设置在栅极电介质膜的顶部上以与半导体层重叠的栅电极。此外，形成第一堤绝缘体以覆盖源电极，形成第二堤绝缘体以覆盖漏电极，并且半导体层，栅极电介质膜和栅极电极嵌入在第一银行绝缘子和第二银行绝缘子。

10. 发明申请

US20070058101A1 Liquid crystal display device 审中-公开
标题翻译：液晶显示装置
公开(公告)号：US20070058101A1
公开(公告)日：2007-03-15
申请号：US11510561
申请日：2006-08-28
申请人： Masahiro Kawasaki , Takeo Shiba , Shuji Imazeki , Masahiko Ando
发明人： Masahiro Kawasaki , Takeo Shiba , Shuji Imazeki , Masahiko Ando
IPC分类号： G02F1/136 , G02F1/1337
CPC分类号： G02F1/1368 , G02F1/133723 , G02F1/133784 , G02F2202/02
摘要： It is an object of the present invention to prevent degradation of an organic semiconductor film caused in forming an alignment layer and to inexpensively provide a liquid crystal display device with a high-performance organic thin film transistor. According to the invention, in a liquid crystal display device that includes: a thin film transistor substrate having such members as a thin film transistor composed of a gate electrode, a gate insulating film, source/drain electrodes, and a semiconductor layer, a line, and a pixel electrode; and an opposing substrate supporting a liquid crystal layer between the thin film transistor substrate and the opposing substrate, no alignment layer having a function of controlling alignment of molecules in the liquid crystal layer is interposed between the semiconductor layer and the liquid crystal layer.
摘要翻译：本发明的目的是防止在形成取向层时引起的有机半导体膜的劣化，并且廉价地提供具有高性能有机薄膜晶体管的液晶显示装置。根据本发明，在液晶显示装置中，包括：薄膜晶体管基板，其具有由栅电极，栅绝缘膜，源/漏电极和半导体层组成的薄膜晶体管的构件，线，和像素电极; 以及在薄膜晶体管基板和对置基板之间支撑液晶层的相对基板，在半导体层和液晶层之间插入不具有控制液晶层中的分子取向功能的取向层。

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