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1. 发明授权

US4103344A Method and apparatus for addressing a non-volatile memory array 失效
标题翻译：用于解决非易失性存储器阵列的方法和装置
公开(公告)号：US4103344A
公开(公告)日：1978-07-25
申请号：US653760
申请日：1976-01-30
申请人： John Lee Fagan , Marvin Hart White , Donald Ross Lampe
发明人： John Lee Fagan , Marvin Hart White , Donald Ross Lampe
IPC分类号： G11C11/34 , G11C16/04 , G11C16/08 , H01L29/792 , G11C11/40
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/08
摘要： A method and apparatus for charge addressing a non-volatile MNOS memory cell in a LSI array of memory cells, is disclosed. Each MNOS cell of the array is made up of a substrate; adjacent diffusion areas in the substrate; a memory window intermediate the adjacent diffusion areas, controlled by a memory gate; and an enable gate adjacent the memory window and overlapping one of the diffusion areas. The memory gate and the enable gate are each separated from the substrate and each other by silicon dioxide/silicon nitride layers to provide a capacitive dielectric. Addressing of an individual cell in the array is achieved by selective activation of a corresponding enable gate and a corresponding memory gate, which are formed in an orthogonal grid array. The cell is accessed by a single stage of a shift register for both read and write operations through a transfer gating means.

2. 发明授权

US4079238A Dual-CCD, real-time, fully-analog correlator 失效
标题翻译：双CCD，实时，全模拟相关器
公开(公告)号：US4079238A
公开(公告)日：1978-03-14
申请号：US625696
申请日：1975-10-24
申请人： Donald Ross Lampe , Marvin Hart White , Hung C. Lin
发明人： Donald Ross Lampe , Marvin Hart White , Hung C. Lin
IPC分类号： G06G7/163 , G06G7/19 , G11C27/04 , H03K5/159
CPC分类号： G11C27/04 , G06G7/163 , G06G7/1907 , H03H2015/026
摘要： The proposed general-purpose, fully-analog device is capable of such functions as auto-correlation, cross-correlation, convolution, transversal filters, etc. at high speeds (one megahertz typical sample rates) with no analog-to-digital or digital-to-analog conversions. The device correlates analog samples in one CCD channel against analog samples in a second CCD channel by means of balanced MOSFET's which multiply the associated voltage samples to give current products that are summed for all multipliers. The two CCD channels include unique floating-clock sensor and buffer circuits which sense the CCD charge samples without affecting the efficiency of their propagation along the CCD shift register. The matched MOSFET multipliers and current summing amplifiers are also uniquely combined in a dual-differential configuration so as to minimize the nondestructive sensing and buffering cells and the matched multiplier cells with the longitudinal dimensions of the CCD, permitting the latter to be small for efficient propagation.
摘要翻译：所提出的通用全模拟器件能够具有高速（一兆赫兹典型采样率）的自相关，互相关，卷积，横向滤波器等功能，无模拟数字或数字模拟转换。该器件通过平衡MOSFET将一个CCD通道中的模拟采样与第二CCD通道中的模拟采样相关联，该平衡MOSFET将相关联的电压采样乘以给出所有乘法器相加的当前乘积。两个CCD通道包括唯一的浮动时钟传感器和缓冲电路，可以感测CCD电荷样本，而不会影响其沿CCD移位寄存器传播的效率。匹配的MOSFET乘法器和电流求和放大器也在双差分配置中独特地组合，以便最小化具有CCD纵向尺寸的非破坏性感测和缓冲单元以及匹配的乘法器单元，从而允许后者为有效传播而小。

3. 发明授权

US4035628A Analog transversal filtering and correlation with progressive summation of analog signals 失效
标题翻译：模拟横向滤波，并与模拟信号的进行求和相关
公开(公告)号：US4035628A
公开(公告)日：1977-07-12
申请号：US625691
申请日：1975-10-24
申请人： Donald Ross Lampe , Marvin Hart White
发明人： Donald Ross Lampe , Marvin Hart White
IPC分类号： G06G7/19 , G11C27/04 , H03H15/02 , H03K5/159 , G11C11/40
CPC分类号： G11C27/04 , G06G7/1907 , H03H15/023
摘要： "Progressive summation" of analog signals with a parallel-in/serial-out (P/I/SO) CCD structure replaces the conventional "simultaneous summation" of analog signals in serial-in/parallel-out (SI/PO) structured systems. Gain non-uniformities presented by buffer circuits and caused in part by threshold non-uniformities are avoided; on-chip power consumption is reduced, thereby avoiding a source of further exaggeration of gain non-uniformities of buffer circuits. Transversal filtering and correlation systems in accordance with the invention accordingly are achieved with these problems of prior art circuits avoided. Reduced power consumption on-chip also maintains more reasonable and constant operating temperature levels, avoiding deleterious effects of temperature increases on dynamic range of CCD systems due to leakage current levels which sharply increase with increased temperature, contributing noise and reducing the maximum charge potential of the CCD wells available for signal.
摘要翻译：具有并行/串行输出（P / I / SO）CCD结构的模拟信号的“逐行求和”取代了串行/并行输出（SI / PO）结构化系统中常规的模拟信号的“同时求和” 。避免缓冲电路提供的不均匀性增加，部分由阈值非均匀性引起; 片上功耗降低，从而避免了进一步夸大缓冲电路增益不均匀性的根源。相应地，根据本发明的横向滤波和相关系统可以通过避免现有技术电路的这些问题来实现。片上功耗降低也保持了更合理和恒定的工作温度水平，避免了由于泄漏电流水平随着温度升高而急剧增加而导致的温度升高对CCD系统的动态范围的有害影响，有助于噪声和降低最大电荷电位 CCD井可用于信号。

4. 发明授权

US4112507A Addressable MNOS cell for non-volatile memories 失效
标题翻译：用于非易失性存储器的可寻址MNOS单元
公开(公告)号：US4112507A
公开(公告)日：1978-09-05
申请号：US653849
申请日：1976-01-30
申请人： Marvin Hart White , Donald Ross Lampe
发明人： Marvin Hart White , Donald Ross Lampe
IPC分类号： G11C16/04 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0466 , H01L29/792
摘要： An addressable MNOS transistor structure is disclosed employing a plurality of gate regions between the source and drain diffusion regions of each transistor cell. The transistor cell is characterized by high and low threshold states which are settable by selective actuation of the corresponding plurality of gate regions. Reading of the state of the transistor is accomplished by applying a read voltage, having a value intermediate the two threshold values, to the corresponding plurality of gate regions and measuring whether or not an applied charge discharges from one diffusion region to the other.
摘要翻译：公开了可寻址的MNOS晶体管结构，其采用在每个晶体管单元的源极和漏极扩散区之间的多个栅极区。晶体管单元的特征在于高和低阈值状态，其可通过相应的多个栅极区域的选择性驱动来设置。通过将具有中间两个阈值的读取电压施加到对应的多个栅极区域并测量施加的电荷是否从一个扩散区域放电到另一个扩散区域来实现对晶体管的状态的读取。

5. 发明授权

US4064533A CCD focal plane processor for moving target imaging 失效
标题翻译： CCD焦平面处理器，用于移动目标成像
公开(公告)号：US4064533A
公开(公告)日：1977-12-20
申请号：US625702
申请日：1975-10-24
申请人： Donald Ross Lampe , Marvin Hart White
发明人： Donald Ross Lampe , Marvin Hart White
IPC分类号： G01S11/12 , G01S13/538 , H01L27/105 , H01L27/148 , H04N5/33 , H04N5/353 , H04N5/372 , H04N7/18 , H01L29/78
CPC分类号： H04N3/1575 , G01S11/12 , G01S13/538 , H01L27/1057 , H01L27/14881 , H04N3/1537 , H04N5/33
摘要： A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to each of the element sensors of the corresponding column of the array. Two "snapshots" of the scene are taken at time-displaced intervals and are compared to detect differences therebetween to eliminate background, or unchanging scene content. The individual sensors provide outputs which are injected into the .alpha. stages of the corresponding paired shift register stages of each CCD shift register in a first time interval corresponding to the first "snapshot". The resulting charge packets in the first (.alpha.) stages then are advanced to the second (.beta.) stages of each shift register pair. The second "snapshot" corresponds to injecting a second signal into the .alpha. stages of the plurality of pairs of .alpha., .beta. stages. The CCD shift registers then are read out simultaneously and in succession as to the plural, related .alpha., .beta. pairs of stages containing the time-displaced elemental signal samples. A further CCD shift register including a number of .alpha., .beta. pairs of stages receives the parallel .alpha., .beta. outputs in corresponding time sequential manner to maintain the .alpha., .beta. related pair arrangement of the time-displaced elemental samples. An output circuit compares the .alpha., .beta. signals for each elemental area and determines the difference therebetween. A CRT display receives the difference signal outputs for displaying moving target information.
摘要翻译：一种CCD焦平面处理器，具有多个具有多列传感元件的独立传感器元件列。该结构包括对应于传感器列数的多个CCD移位寄存器，每个CCD移位寄存器包括与阵列的相应列的每个元件传感器对应的一对级。以时间间隔采取场景的两个“快照”，并将其进行比较以检测其间的差异以消除背景或不变的场景内容。各个传感器在对应于第一“快照”的第一时间间隔内提供注入每个CCD移位寄存器的相应配对移位寄存器级的α级的输出。然后，在第一（α）级中产生的电荷包被提前到每个移位寄存器对的第二（β）级。第二“快照”对应于将第二信号注入到多对α，β级的α级中。然后，对于包含时间偏移的元素信号样本的多个相关的α，β对的阶段，CCD移位寄存器被连续读出。包括多个α，β对级数的另外的CCD移位寄存器以相应的时间顺序方式接收并行α，β输出，以维持时间偏移元素样本的α，β相关对排列。输出电路比较每个元件区域的α，β信号，并确定它们之间的差异。 CRT显示器接收用于显示移动目标信息的差分信号输出。

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