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1. 发明授权

US08712360B2 System and transceiver clocking to minimize required number of reference sources in multi-function cellular applications including GPS 有权
标题翻译：系统和收发器时钟，以最小化包括GPS在内的多功能蜂窝应用中所需的参考源数量
公开(公告)号：US08712360B2
公开(公告)日：2014-04-29
申请号：US14021339
申请日：2013-09-09
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Alexander Zaslavsky , Brian T. Brunn
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.
摘要翻译：系统包括第一时钟模块，全球定位系统（GPS）模块，锁相环（PLL）模块，蜂窝收发器和基带模块。第一个时钟模块生成第一个时钟参考。 GPS模块响应于第一个时钟参考而工作。 WLAN模块响应于第一个时钟参考而工作。 PLL模块通过响应于AFC信号在第一时钟参考上执行自动频率校正（AFC）来产生第二时钟参考。蜂窝收发器从无线介质接收射频信号，并响应于所接收的射频信号产生基带信号。基带模块接收基带信号，响应于第一时钟参考和第二时钟参考中的所选择的一个而工作，并响应于基带信号产生AFC信号。

2. 发明申请

US20130052966A1 System and Transceiver Clocking to Minimize Required Number of Reference Sources in Multi-Function Cellular Applications Including GPS 有权
标题翻译：系统和收发器时钟，以最小化包含GPS的多功能蜂窝应用中所需的参考源数量
公开(公告)号：US20130052966A1
公开(公告)日：2013-02-28
申请号：US13664309
申请日：2012-10-30
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Alexander Zaslavsky , Brian Brunn
IPC分类号： H04W88/02
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.
摘要翻译：系统包括第一时钟模块，全球定位系统（GPS）模块，锁相环（PLL）模块，蜂窝收发器和基带模块。第一个时钟模块生成第一个时钟参考。 GPS模块响应于第一个时钟参考而工作。 WLAN模块响应于第一个时钟参考而工作。 PLL模块通过响应于AFC信号在第一时钟参考上执行自动频率校正（AFC）来产生第二时钟参考。蜂窝收发器从无线介质接收射频信号，并响应于所接收的射频信号产生基带信号。基带模块接收基带信号，响应于第一时钟参考和第二时钟参考中的所选择的一个而工作，并响应于基带信号产生AFC信号。

3. 发明授权

US09214923B2 Wireless communications system including dual-purpose clock reference for global positioning system and baseband 有权
标题翻译：无线通信系统包括用于全球定位系统和基带的双用途时钟参考
公开(公告)号：US09214923B2
公开(公告)日：2015-12-15
申请号：US14705320
申请日：2015-05-06
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Alexander Zaslavsky , Brian T. Brunn
IPC分类号： H04B1/06 , H04B7/00 , H03J7/02 , H04B1/16 , G01S19/23 , H04W84/12
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A wireless communications system includes a clock module, a global positioning system (GPS) module, an integrated circuit for a cellular transceiver, and a baseband module. The clock module is configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). The GPS module is configured to operate in response to the first clock reference. The integrated circuit includes a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference, and (ii) generate a corrected clock reference by performing AFC on the first clock reference in response to an AFC signal. The baseband module is configured to (i) operate in response to the first clock reference from the clock module, and (ii) generate the AFC signal.
摘要翻译：无线通信系统包括时钟模块，全球定位系统（GPS）模块，用于蜂窝收发器的集成电路和基带模块。时钟模块被配置为生成不使用自动频率校正（AFC）校正的第一时钟基准。 GPS模块被配置为响应于第一时钟参考而工作。集成电路包括被配置为（i）响应于第一时钟参考而操作的系统锁相环（PLL），以及（ii）通过响应于AFC信号在第一时钟基准上执行AFC来产生校正时钟参考。基带模块被配置为（i）响应于来自时钟模块的第一时钟参考而操作，以及（ii）生成AFC信号。

4. 发明授权

US09054677B2 Clock multiplexing for baseband automatic frequency correction 有权
标题翻译：用于基带自动频率校正的时钟复用
公开(公告)号：US09054677B2
公开(公告)日：2015-06-09
申请号：US14263492
申请日：2014-04-28
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Alexander Zaslavsky , Brian T. Brunn
IPC分类号： H04B1/06 , H04B7/00 , H03J7/02 , G01S19/23 , H03J1/00 , H03J7/04 , H03L7/197 , H03L7/22 , H03L7/08 , H04B1/16
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.
摘要翻译：无线通信系统包括时钟模块，通信模块，接收模块和基带模块。时钟模块被配置为生成第一个时钟参考。通信模块被配置为响应于第一时钟参考而操作，并且独立于校正的时钟参考。通过根据自动频率校正信号对第一时钟基准执行自动频率校正来产生校正的时钟基准。接收器模块被配置为（i）从无线介质接收射频信号，以及（ii）响应于校正的时钟参考，基于所接收的射频信号产生基带信号。基带模块被配置为（i）接收基带信号，以及（ii）响应于所选择的第一时钟参考和校正时钟参考中的一个，基于基带信号生成自动频率校正信号。

5. 发明授权

US09042859B2 Dual carrier amplifier circuits and methods 有权
标题翻译：双载波放大器电路及方法
公开(公告)号：US09042859B2
公开(公告)日：2015-05-26
申请号：US13936400
申请日：2013-07-08
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Xiaohua Fan
IPC分类号： H04B1/26 , H03H11/04 , H03F1/22 , H03F3/45 , H03F3/72
CPC分类号： H03H11/0461 , H03F1/223 , H03F3/45076 , H03F3/72 , H03F2200/222 , H03F2200/294 , H03F2200/414 , H03F2200/429 , H03F2200/451 , H03F2203/45352 , H03F2203/45366 , H03F2203/45394 , H03F2203/45464 , H03F2203/7209 , H03F2203/7236
摘要： A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.
摘要翻译：电路包括分别响应于输入信号产生第一和第二电流的第一和第二跨导级。当前组合器电路选择性地将第一电流耦合到第一输出端，选择性地将第二电流耦合到第一输出端，选择性地将第一电流耦合到第二输出，并且选择性地将第二电流耦合到第二输出端。响应于第一电流耦合到第一和第二输出，当前组合器电路将第二电流耦合到第一和第二输出。响应于第一电流与第二输出端分离，当前组合器电路使第二电流与第一和第二输出端分离。响应于第一电流与第一输出端分离，当前组合器电路使第二电流与第一和第二输出端分离。

6. 发明授权

US08831143B2 DC offset cancellation in direct conversion receivers 有权
标题翻译：直接转换接收机中的直流偏移消除
公开(公告)号：US08831143B2
公开(公告)日：2014-09-09
申请号：US14138074
申请日：2013-12-22
申请人： Marvell World Trade Ltd.
发明人： Rony Ashkenazi , Alexander Zaslavsky , Gregory Uehara , Brian Brunn
IPC分类号： H04L25/06
CPC分类号： H04L25/061 , H04B1/30
摘要： A method for DC offset cancellation includes defining, in a range of possible gain values for operating a direct conversion receiver, multiple sub-ranges of the possible gain values. Multiple DC offset correction values for the respective sub-ranges are stored in a memory. Upon detecting at the receiver that a gain of the receiver has changed from a first sub-range to a second sub-range, DC offset cancellation is initiated based on a DC offset correction value stored for the second sub-range and on a condition relating to past operation in the second sub-range.
摘要翻译：用于DC偏移消除的方法包括在用于操作直接转换接收器的可能增益值的范围内定义可能增益值的多个子范围。各个子范围的多个DC偏移校正值被存储在存储器中。在接收机检测到接收机的增益已经从第一子范围改变到第二子范围时，基于对于第二子范围存储的DC偏移校正值以及关于第二子范围的条件启动DC偏移消除过去在第二个子范围内的操作。

7. 发明授权

US08787511B2 Frequency and Q-factor tunable filters using frequency translatable impedance structures 有权
标题翻译：频率和Q因子可调滤波器使用频率可调阻抗结构
公开(公告)号：US08787511B2
公开(公告)日：2014-07-22
申请号：US14060119
申请日：2013-10-22
申请人： Marvell World Trade Ltd.
发明人： Brian Brunn , Gregory Uehara , Sehat Sutardja
IPC分类号： H04B1/10
CPC分类号： H04B1/109 , H04B1/1036
摘要： A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.
摘要翻译：包括滤波器和下变频器的系统。滤波器被配置为从节点接收（i）第一信号和（ii）第二信号，并且对第二信号进行滤波。滤波器包括第一输入阻抗。滤波器包括第一多个开关和第一电路。第一多个交换机被配置为与节点通信。第一多个开关以第一频率被计时。第一频率基于第一信号的频率。第一电路被配置为与多个开关的输出通信。第一电路包括第二输入阻抗。第二输入阻抗与第一输入阻抗不同。下变频器被配置为（i）接收第一信号和（ii）下变频第一信号。滤波器和下变频器与节点并联连接。

8. 发明申请

US20140044224A1 FREQUENCY AND Q-FACTOR TUNABLE FILTERS USING FREQUENCY TRANSLATABLE IMPEDANCE STRUCTURES 有权
标题翻译：使用频率可转换阻抗结构的频率和Q因子滤波器
公开(公告)号：US20140044224A1
公开(公告)日：2014-02-13
申请号：US14060119
申请日：2013-10-22
申请人： Marvell World Trade Ltd.
发明人： Brian Brunn , Gregory Uehara , Sehat Sutardja
IPC分类号： H04B1/10
CPC分类号： H04B1/109 , H04B1/1036
摘要： A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.
摘要翻译：包括滤波器和下变频器的系统。滤波器被配置为从节点接收（i）第一信号和（ii）第二信号，并且对第二信号进行滤波。滤波器包括第一输入阻抗。滤波器包括第一多个开关和第一电路。第一多个交换机被配置为与节点通信。第一多个开关以第一频率被计时。第一频率基于第一信号的频率。第一电路被配置为与多个开关的输出通信。第一电路包括第二输入阻抗。第二输入阻抗与第一输入阻抗不同。下变频器被配置为（i）接收第一信号和（ii）下变频第一信号。滤波器和下变频器与节点并联连接。

9. 发明申请

US20140011467A1 System And Transceiver Clocking To Minimize Required Number Of Reference Sources In Multi-Function Cellular Applications Including GPS 有权
标题翻译：系统和收发器时钟在包括GPS的多功能蜂窝应用中最小化所需的参考源数量
公开(公告)号：US20140011467A1
公开(公告)日：2014-01-09
申请号：US14021339
申请日：2013-09-09
申请人： Marvell World Trade Ltd.
发明人： Gregory Uehara , Alexander Zaslavsky , Brian T. Brunn
IPC分类号： H03L7/08
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.
摘要翻译：系统包括第一时钟模块，全球定位系统（GPS）模块，锁相环（PLL）模块，蜂窝收发器和基带模块。第一个时钟模块生成第一个时钟参考。 GPS模块响应于第一个时钟参考而工作。 WLAN模块响应于第一个时钟参考而工作。 PLL模块通过响应于AFC信号在第一时钟参考上执行自动频率校正（AFC）来产生第二时钟参考。蜂窝收发器从无线介质接收射频信号，并响应于所接收的射频信号产生基带信号。基带模块接收基带信号，响应于第一时钟参考和第二时钟参考中的所选择的一个而工作，并响应于基带信号产生AFC信号。

10. 发明申请

US20130244598A1 MODULAR FREQUENCY DIVIDER AND MIXER CONFIGURATION 审中-公开
标题翻译：模块化分频器和混频器配置
公开(公告)号：US20130244598A1
公开(公告)日：2013-09-19
申请号：US13892818
申请日：2013-05-13
申请人： MARVELL WORLD TRADE LTD.
发明人： Danilo Gerna , Stefano Dal Toso , Gregory Uehara
IPC分类号： H04B1/04
CPC分类号： H04B1/0483 , H03B19/00 , H03K23/667 , H03L7/18 , H04B2001/0491
摘要： A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.
摘要翻译：一种发射机，包括第一混频器，第一分频器，用于分频输入信号的频率以产生第一信号，以及多个第二分频器，以分频以分别产生多个第二信号;以及控制模块。响应于发射机被接通，控制模块接通第一分频器，关闭多个第二分频器，并用第一信号驱动第一混频器。随后，响应于确定要增加发射机的发射功率，控制模块顺序地接通并连接多个第二分频器中的每一个与第一分频器并联。当第二分频器连接到第一分频器时，控制模块还使用由第二分频器产生的第二信号来驱动第一混频器。

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