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1. 发明申请

US20100095094A1 METHOD FOR PROCESSING DATA 审中-公开
标题翻译：数据处理方法
公开(公告)号：US20100095094A1
公开(公告)日：2010-04-15
申请号：US12640201
申请日：2009-12-17
申请人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
发明人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
IPC分类号： G06F9/30
CPC分类号： G06F8/45 , G06F15/7867
摘要： A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
摘要翻译：一种用于将程序转换为包括至少一个第一处理器和可重构单元的系统的方法和装置。确定适合于可重构单元的程序的代码部分。程序的剩余代码被提取和/或分离以供第一处理器处理。

2. 发明授权

US07657877B2 Method for processing data 有权
标题翻译：数据处理方法
公开(公告)号：US07657877B2
公开(公告)日：2010-02-02
申请号：US10480003
申请日：2002-06-20
申请人： Martin Vorbach , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
发明人： Martin Vorbach , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
IPC分类号： G06F9/44
CPC分类号： G06F8/45 , G06F15/7867
摘要： A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
摘要翻译：一种用于将程序转换为包括至少一个第一处理器和可重构单元的系统的方法和装置。确定适合于可重构单元的程序的代码部分。程序的剩余代码被提取和/或分离以供第一处理器处理。

3. 发明授权

US08869121B2 Method for the translation of programs for reconfigurable architectures 有权
标题翻译：翻译可重构架构程序的方法
公开(公告)号：US08869121B2
公开(公告)日：2014-10-21
申请号：US13177820
申请日：2011-07-07
申请人： Martin Vorbach , Frank May , Armin Nückel
发明人： Martin Vorbach , Frank May , Armin Nückel
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.
摘要翻译：描述使用多维字段的数据处理以及有利地使用高级语言代码的方法。

4. 发明授权

US08058899B2 Logic cell array and bus system 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US08058899B2
公开(公告)日：2011-11-15
申请号：US12371040
申请日：2009-02-13
申请人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： H03K19/199 , G06F7/52
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

5. 发明申请

US20120311301A1 PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US20120311301A1
公开(公告)日：2012-12-06
申请号：US13491894
申请日：2012-06-08
申请人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.
摘要翻译：在一种使处理器装置的数据处理同步的方法中，响应于在程序执行期间到达包括在程序序列中的屏障，处理器装置停止程序执行，直到确定程序序列中的屏障之前的所有指令已经成功安排执行。

6. 发明授权

US08471593B2 Logic cell array and bus system 有权
公开(公告)号：US08471593B2
公开(公告)日：2013-06-25
申请号：US13289296
申请日：2011-11-04
申请人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： G06F7/52
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

7. 发明授权

US08468329B2 Pipeline configuration protocol and configuration unit communication 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US08468329B2
公开(公告)日：2013-06-18
申请号：US13491894
申请日：2012-06-08
申请人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F11/07
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.
摘要翻译：在一种使处理器装置的数据处理同步的方法中，响应于在程序执行期间到达包括在程序序列中的屏障，处理器装置停止程序执行，直到确定程序序列中的屏障之前的所有指令已经成功安排执行。

8. 发明申请

US20090210653A1 METHOD AND DEVICE FOR TREATING AND PROCESSING DATA 审中-公开
标题翻译：用于处理和处理数据的方法和设备
公开(公告)号：US20090210653A1
公开(公告)日：2009-08-20
申请号：US12389116
申请日：2009-02-19
申请人： Martin Vorbach , Volker Baumgarte , Armin Nückel , Frank May
发明人： Martin Vorbach , Volker Baumgarte , Armin Nückel , Frank May
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/8046
摘要： Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data streams being recombined in the correct sequence. This method may be particularly useful for executing reentrant code. The method is well suited, in particular, for configurable architectures; particular attention is paid to the efficient control of configuration and reconfiguration.
摘要翻译：描述了在发射机和接收机的多维系统内管理和传输数据的过程和方法。将数据流分解成多个独立分支并且随后各个分支的合并以形成数据流可以以简单的方式执行，单个数据流以正确的顺序重新组合。该方法对于执行可重入代码可能特别有用。该方法特别适用于可配置架构; 特别注意配置和重新配置的有效控制。

9. 发明申请

US20120072699A1 LOGIC CELL ARRAY AND BUS SYSTEM 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US20120072699A1
公开(公告)日：2012-03-22
申请号：US13289296
申请日：2011-11-04
申请人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

10. 发明授权

US07266725B2 Method for debugging reconfigurable architectures 有权
标题翻译：调试可重构架构的方法
公开(公告)号：US07266725B2
公开(公告)日：2007-09-04
申请号：US09967497
申请日：2001-09-28
申请人： Martin Vorbach , Frank May , Armin Nückel
发明人： Martin Vorbach , Frank May , Armin Nückel
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method for efficiently debugging a program defining a plurality of configurations to be successively processed on a dynamically reconfigurable architecture including a plurality of logic elements cooperating with each other. The method includes storing data in a memory in a configuration-conforming manner, the data generated by executing a configuration forming part of the program on the reconfigurable architecture, and including algorithmically relevant state data of the program that is associated with at least one of the configurations. The method further includes subsequently continuing execution of the program, the execution including a reconfiguration, and detecting an error based on stored state data, wherein for each state for which corresponding state data is to be stored, the state remains unchanged at least until the corresponding state data is stored. For obtaining a particular state data, the method interrupts execution of the program by configuring a first configuration via which the particular state data is transmitted to a debugging unit instead of a second configuration that is a next-required configuration of the program; and subsequent to obtaining the particular state data, resumes execution of the program by configuring the second configuration.
摘要翻译：一种用于有效地调试定义要在包括彼此协作的多个逻辑元件的动态可重构架构上连续处理的多个配置的程序的方法。该方法包括以符合配置的方式将数据存储在存储器中，所述数据通过执行在所述可重构架构上形成所述程序的一部分的配置而生成，并且包括与所述程序的至少一个相关联的所述程序的与算法相关的状态数据配置该方法还包括随后继续执行程序，执行包括重新配置，并且基于存储的状态数据检测错误，其中对于要对其存储对应的状态数据的每个状态，状态至少保持不变，直到相应的状态数据被存储。为了获得特定状态数据，该方法通过配置将特定状态数据发送到调试单元而不是作为程序的下一个所需配置的第二配置的第一配置来中断程序的执行; 并且在获得特定状态数据之后，通过配置第二配置来恢复程序的执行。

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