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1. 发明申请

US20080217672A1 INTEGRATED CIRCUIT HAVING A MEMORY 审中-公开
标题翻译：具有存储器的集成电路
公开(公告)号：US20080217672A1
公开(公告)日：2008-09-11
申请号：US11684033
申请日：2007-03-09
申请人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
发明人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
IPC分类号： H01G4/40 , H01L21/62 , H01L27/01
CPC分类号： H01L27/10817 , H01G4/38 , H01G4/40 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10888 , H01L28/91
摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.
摘要翻译：公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

2. 发明授权

US07727837B2 Method of producing an integrated circuit having a capacitor with a supporting layer 失效
标题翻译：一种具有带支撑层的电容器的集成电路的制造方法
公开(公告)号：US07727837B2
公开(公告)日：2010-06-01
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

3. 发明申请

US20080182378A1 METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR 失效
标题翻译：生产具有电容器的集成电路的方法
公开(公告)号：US20080182378A1
公开(公告)日：2008-07-31
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

4. 发明授权

US07449739B2 Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor 失效
标题翻译：用于半导体存储单元的存储电容器和制造存储电容器的方法
公开(公告)号：US07449739B2
公开(公告)日：2008-11-11
申请号：US11339744
申请日：2006-01-25
申请人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
发明人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10852
摘要： A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.
摘要翻译：公开了用于动态半导体存储器单元的电容器，存储器和制造存储器的方法。在一个实施例中，电容器的存储电极具有衬垫形下部和杯形上部，其放置在下部的顶部。背面电极的下部包围存储电极的垫状部分。背面电极的上部被储存电极的杯状上部包围。第一电容器介质分离背面的下部和存储电极。第二电容器电介质将背面的上部和存储电极分开。电容器的电极面积被放大，而电容器电介质沉积的要求被放宽。降低沉积和蚀刻工艺的长宽比。

5. 发明申请

US20070170487A1 Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor 失效
标题翻译：用于半导体存储单元的存储电容器和制造存储电容器的方法
公开(公告)号：US20070170487A1
公开(公告)日：2007-07-26
申请号：US11339744
申请日：2006-01-25
申请人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
发明人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.
摘要翻译：公开了用于动态半导体存储器单元的电容器，存储器和制造存储器的方法。在一个实施例中，电容器的存储电极具有衬垫形下部和杯形上部，其放置在下部的顶部。背面电极的下部包围存储电极的垫状部分。背面电极的上部被储存电极的杯状上部包围。第一电容器介质分离背面的下部和存储电极。第二电容器电介质将背面的上部和存储电极分开。电容器的电极面积被放大，而电容器电介质沉积的要求被放宽。降低沉积和蚀刻工艺的长宽比。

6. 发明申请

US20070286945A1 METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A MOLD LAYER 有权
标题翻译：形成集成电路的方法，包括模具层中的开口
公开(公告)号：US20070286945A1
公开(公告)日：2007-12-13
申请号：US11687426
申请日：2007-03-16
申请人： Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
发明人： Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
IPC分类号： B05D5/12 , B05D5/00
CPC分类号： H01L28/40 , H01L27/10861 , Y10S977/70 , Y10S977/72
摘要： A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.
摘要翻译：公开了一种在模具层中形成具有开口并用于制造电容器的集成电路的方法。在一个实施例中，纳米管或纳米线在水平衬底表面上垂直生长。纳米管或纳米线用作在模具层中形成开口的模板。在形成纳米线或纳米管之后，用模具材料覆盖基底。一个实施例提供了具有高得多的纵横比的开口的模具层。

7. 发明授权

US07776759B2 Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes 有权
标题翻译：用于形成集成电路的方法，包括来自纳米线或纳米管的模具层中的开口
公开(公告)号：US07776759B2
公开(公告)日：2010-08-17
申请号：US11687426
申请日：2007-03-16
申请人： Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
发明人： Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
IPC分类号： B82B1/00 , H01L29/92 , B82B3/00
CPC分类号： H01L28/40 , H01L27/10861 , Y10S977/70 , Y10S977/72
摘要： A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.
摘要翻译：公开了一种在模具层中形成具有开口并用于制造电容器的集成电路的方法。在一个实施例中，纳米管或纳米线在水平衬底表面上垂直生长。纳米管或纳米线用作在模具层中形成开口的模板。在形成纳米线或纳米管之后，用模具材料覆盖基底。一个实施例提供了具有高得多的纵横比的开口的模具层。

8. 发明授权

US07615444B2 Method for forming a capacitor structure 失效
标题翻译：形成电容器结构的方法
公开(公告)号：US07615444B2
公开(公告)日：2009-11-10
申请号：US11477581
申请日：2006-06-29
申请人： Odo Wunnicke , Peter Moll , Kristin Schupke
发明人： Odo Wunnicke , Peter Moll , Kristin Schupke
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10808 , H01L27/10852
摘要： A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.
摘要翻译：一种用于形成电容器结构的方法，根据该方法执行以下连续步骤：提供在其表面上具有接触焊盘的基板和设置有至少一个沟槽的介电模，留下暴露的接触焊盘; 在所述沟槽的顶部区域中在所述沟槽的侧壁上形成第一导电层，所述导电层不与所述接触焊盘接触; 沉积第一介电层; 在所述接触焊盘和所述沟槽的侧壁上沉积第二导电层; 沉积第二电介质层; 沉积第三导电层; 以及形成互连所述第一导电层和所述第三导电层的垂直插头。

9. 发明授权

US09887313B2 Method for producing differently doped semiconductors 有权
公开(公告)号：US09887313B2
公开(公告)日：2018-02-06
申请号：US15307689
申请日：2015-04-17
申请人： Christoph Mader , Christian Guenther , Joachim Erz , Susanne Christine Martens , Jasmin Lehmkuhl , Stephan Traut , Odo Wunnicke
发明人： Christoph Mader , Christian Guenther , Joachim Erz , Susanne Christine Martens , Jasmin Lehmkuhl , Stephan Traut , Odo Wunnicke
IPC分类号： H01L21/00 , H01L31/18 , H01L21/22 , H01L21/228
CPC分类号： H01L31/1804 , H01L21/2225 , H01L21/228 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： The present invention relates to a liquid-phase method for doping a semiconductor substrate, characterized in that a first composition containing at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the first composition; a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the second composition, where the one or more region(s) coated with the first composition and the one or more region(s) coated with the second composition are different and do not overlap significantly and where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; the regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each fully or partly activated; optionally, the unactivated regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each oxidized; and the semiconductor substrate is heated to a temperature at which the dopants diffuse out of the coating into the semiconductor substrate. The invention further relates to the semiconductor obtainable by the method and to the use thereof, especially in the production of solar cells.

10. 发明授权

US07544562B2 Method for manufacturing a capacitor electrode structure 失效
标题翻译：电容器电极结构的制造方法
公开(公告)号：US07544562B2
公开(公告)日：2009-06-09
申请号：US11489052
申请日：2006-07-19
申请人： Peter Moll , Odo Wunnicke
发明人： Peter Moll , Odo Wunnicke
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/8242
CPC分类号： H01G4/005 , H01G4/33 , H01L27/0207 , H01L27/10852 , H01L28/60
摘要： A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls. And a conductive layer is applied on the first and second supporting walls for forming a first electrode of the capacitor structure.
摘要翻译：一种用于制造电容器电极结构的方法，根据该方法执行以下步骤：提供基板，其包括在所述基板的表面上以行和行排列的接触焊盘。线条与行不平行。将第一模具施加在基板上。在接触垫上方的第一模具中形成至少一个第一沟槽。第一沟槽跨越排列成一行的至少两个接触垫。第一电介质层被施加在用于形成第一支撑壁的至少一个第一沟槽的侧壁上。在基板上施加第二模具。在接触垫上方的第二模具中形成至少一个第二沟槽。第二沟槽跨越排列成一行的至少两个接触垫。第二介电层施加在至少一个第二沟槽的侧壁上，用于形成第二支撑壁。并且在第一和第二支撑壁上施加导电层以形成电容器结构的第一电极。

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