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1. 发明授权

US07119395B2 Memory cell with nanocrystals or nanodots 有权
标题翻译：具有纳米晶体或纳米点的记忆体
公开(公告)号：US07119395B2
公开(公告)日：2006-10-10
申请号：US10916013
申请日：2004-08-11
申请人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
发明人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).
摘要翻译：存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。栅电极（5）通过导电间隔物（7）在侧面加宽。

2. 发明申请

US20050067659A1 Memory cell with nanocrystals or nanodots 有权
标题翻译：具有纳米晶体或纳米点的记忆体
公开(公告)号：US20050067659A1
公开(公告)日：2005-03-31
申请号：US10916013
申请日：2004-08-11
申请人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
发明人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).
摘要翻译：存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。栅电极（5）通过导电间隔物（7）在侧面加宽。

3. 发明申请

US20060071244A1 Switching or amplifier device, in particular transistor 审中-公开
标题翻译：开关或放大器器件，特别是晶体管
公开(公告)号：US20060071244A1
公开(公告)日：2006-04-06
申请号：US11188107
申请日：2005-07-25
申请人： Martin Gutsche , Cay-Uwe Pinnow
发明人： Martin Gutsche , Cay-Uwe Pinnow
IPC分类号： H01L29/768
CPC分类号： H01L45/06 , H01L29/685 , H01L45/085 , H01L45/1206 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： The invention relates to a method for operating a switching or amplifier device (11, 111), and to a switching or amplifier device (11, 111) comprising: an active material (13, 113) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts (12a, 12b, 12c).
摘要翻译：本发明涉及一种用于操作开关或放大器装置（11,111）以及开关或放大器装置（11,111）的方法，包括：活动材料（13,113），其适于被放置在或多或少通过适当的切换过程导通状态; 和至少三个电极或触点（12a，12b，12c）。

4. 发明申请

US20050067634A1 Nonvolatile integrated semiconductor memory 失效
标题翻译：非易失性集成半导体存储器
公开(公告)号：US20050067634A1
公开(公告)日：2005-03-31
申请号：US10950477
申请日：2004-09-28
申请人： Cay-Uwe Pinnow , Martin Gutsche , Harald Seidl , Thomas Happ
发明人： Cay-Uwe Pinnow , Martin Gutsche , Harald Seidl , Thomas Happ
IPC分类号： G03G15/02 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/7881 , Y10S438/954
摘要： A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.
摘要翻译：非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。隧道势垒层具有高能电荷载流子穿过的材料。电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

5. 发明授权

US07348619B2 Ferroelectric memory arrangement 失效
标题翻译：铁电存储器布置
公开(公告)号：US07348619B2
公开(公告)日：2008-03-25
申请号：US11216678
申请日：2005-08-31
申请人： Rainer Bruchhaus , Martin Gutsche , Cay-Uwe Pinnow
发明人： Rainer Bruchhaus , Martin Gutsche , Cay-Uwe Pinnow
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C11/22 , G11C11/221 , H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
摘要翻译：具有存储单元的铁电存储器装置，其中每个具有垂直电极和垂直电极之间的铁电电介质的垂直铁电存储电容器连接到选择晶体管，铁电介质在多个铁电层之间，其布置有绝缘分离层。

6. 发明授权

US07084454B2 Nonvolatile integrated semiconductor memory 失效
标题翻译：非易失性集成半导体存储器
公开(公告)号：US07084454B2
公开(公告)日：2006-08-01
申请号：US10950477
申请日：2004-09-28
申请人： Cay-Uwe Pinnow , Martin Gutsche , Harald Seidl , Thomas Happ
发明人： Cay-Uwe Pinnow , Martin Gutsche , Harald Seidl , Thomas Happ
IPC分类号： H01L29/76
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/7881 , Y10S438/954
摘要： A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.
摘要翻译：非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。隧道势垒层具有高能电荷载流子穿过的材料。电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

7. 发明申请

US20060049440A1 Ferroelectric memory arrangement 失效
标题翻译：铁电存储器布置
公开(公告)号：US20060049440A1
公开(公告)日：2006-03-09
申请号：US11216678
申请日：2005-08-31
申请人： Rainer Bruchhaus , Martin Gutsche , Cay-Uwe Pinnow
发明人： Rainer Bruchhaus , Martin Gutsche , Cay-Uwe Pinnow
IPC分类号： H01L29/94
CPC分类号： G11C11/22 , G11C11/221 , H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
摘要翻译：具有存储单元的铁电存储器装置，其中每个具有垂直电极和垂直电极之间的铁电电介质的垂直铁电存储电容器连接到选择晶体管，铁电介质在多个铁电层之间，其布置有绝缘分离层。

8. 发明申请

US20060186480A1 Charge-trapping memory device and method for production 失效
标题翻译：电荷捕获存储器件及其制造方法
公开(公告)号：US20060186480A1
公开(公告)日：2006-08-24
申请号：US11061314
申请日：2005-02-18
申请人： Harald Seidl , Josef Willer , Martin Gutsche
发明人： Harald Seidl , Josef Willer , Martin Gutsche
IPC分类号： H01L31/072 , H01L21/8238
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L29/4234
摘要： A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.
摘要翻译：提供薄SiGe层作为附加的下栅电极层，并且布置在薄栅极氧化物和栅电极层之间，优选多晶硅。 SiGe层可以选择性地蚀刻到栅电极和栅极氧化物，并且在源极/漏极区附近被横向去除以形成凹槽，随后填充适合于电荷捕获的材料。器件结构和制造方法适用于包括存储器单元的本地互连，CMOS逻辑外围和补偿阵列和外围中的层级差异的装置的集成方案。

9. 发明授权

US07186607B2 Charge-trapping memory device and method for production 失效
标题翻译：电荷捕获存储器件及其制造方法
公开(公告)号：US07186607B2
公开(公告)日：2007-03-06
申请号：US11061314
申请日：2005-02-18
申请人： Harald Seidl , Josef Willer , Martin Gutsche
发明人： Harald Seidl , Josef Willer , Martin Gutsche
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L29/4234
摘要： A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.
摘要翻译：提供薄SiGe层作为附加的下栅电极层，并且布置在薄栅极氧化物和栅电极层之间，优选多晶硅。 SiGe层可以选择性地蚀刻到栅电极和栅极氧化物，并且在源极/漏极区附近被横向去除以形成凹槽，随后填充适合于电荷捕获的材料。器件结构和制造方法适用于包括存储器单元的本地互连，CMOS逻辑外围和补偿阵列和外围中的层级差异的装置的集成方案。

10. 发明申请

US20100006983A1 PROCESS FOR PRODUCING SUBLITHOGRAPHIC STRUCTURES 有权
标题翻译：生产分层结构的方法
公开(公告)号：US20100006983A1
公开(公告)日：2010-01-14
申请号：US12548723
申请日：2009-08-27
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L29/00
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/30604
摘要： A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures
摘要翻译：提供了用于提供亚光刻结构的层结构和工艺。在载体层的表面上形成第一辅助层。在第一辅助层的表面上形成光刻图案化的第二辅助层结构。使用图案化的第二辅助层结构作为掩模对第一辅助层进行各向异性蚀刻，以形成各向异性图案化的第一辅助层结构。各向异性图案化的第一辅助层结构使用图案化的第二辅助层结构进行各向同性地回蚀，以除去第二辅助层结构之下的部分并形成各向同性图案化的第一辅助层结构。掩模层形成在载体层上，包括第二辅助层结构下面的子部分，并且各向异性地向下蚀刻到载体层以形成亚光刻结构。去除第一和第二辅助层结构以露出亚光刻结构

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