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1. 发明授权

US09459927B2 Central office based virtual personal computer 有权
标题翻译：中央办公室虚拟个人电脑
公开(公告)号：US09459927B2
公开(公告)日：2016-10-04
申请号：US12125315
申请日：2008-05-22
申请人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
发明人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： G06F9/455 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5077 , G06F9/4856
摘要： A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.
摘要翻译：在包括多个中心局的通信系统中实现虚拟个人计算机，每个中心局通过相应的接入网络与多个客户端设备进行通信。给定的一个中心局包括至少一个计算服务器和至少一个存储服务器。通过将计算服务器的物理处理资源和存储服务器的物理存储资源分配给该虚拟个人计算机来配置虚拟个人计算机。用户访问通过其中一个客户端设备提供给虚拟个人计算机。响应于用户选择的在给定的虚拟个人计算机上运行的特定应用，可以通过将物理处理资源和物理存储资源中的至少一个的分配改变到给定的虚拟个人计算机来动态地重新配置虚拟个人计算机。

2. 发明申请

US20090293055A1 Central Office Based Virtual Personal Computer 有权
标题翻译：中央办公室虚拟个人电脑
公开(公告)号：US20090293055A1
公开(公告)日：2009-11-26
申请号：US12125315
申请日：2008-05-22
申请人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
发明人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： G06F9/455
CPC分类号： G06F9/5077 , G06F9/4856
摘要： A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.
摘要翻译：在包括多个中心局的通信系统中实现虚拟个人计算机，每个中心局通过相应的接入网络与多个客户端设备进行通信。给定的一个中心局包括至少一个计算服务器和至少一个存储服务器。通过将计算服务器的物理处理资源和存储服务器的物理存储资源分配给该虚拟个人计算机来配置虚拟个人计算机。用户访问通过其中一个客户端设备提供给虚拟个人计算机。响应于用户选择的在给定的虚拟个人计算机上运行的特定应用，可以通过将物理处理资源和物理存储资源中的至少一个的分配改变到给定的虚拟个人计算机来动态地重新配置虚拟个人计算机。

3. 发明申请

US20140126919A1 Method And Apparatus For Processing Bit-Interleaved Data Traffic In A Communication Network 有权
标题翻译：在通信网络中处理位交错数据流量的方法和装置
公开(公告)号：US20140126919A1
公开(公告)日：2014-05-08
申请号：US13853754
申请日：2013-03-29
申请人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
发明人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
IPC分类号： H04B10/66
CPC分类号： H04L25/03866 , H04L1/0071
摘要： A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.
摘要翻译：在通信网络中处理比特交织的数据业务的方式。在越来越常见的情况下，在从发送器发送到接收器之前，使用PRBS（伪随机二进制序列）将数据业务进行比特交织和加扰，接收器被配置为接收所发送的比特流并对其进行抽取，是在解扰之前去除分配给接收机的比特流的比特。为了实现这一点，接收机采用与发送方使用的LFSR（线性反馈移位寄存器）类似或相同的数据来加扰数据。通过使用由发送者或初始化单元插入的辅助位来初始化LFSR，并且可以根据发送的比特流的性质使用用于相位调整或状态跳过的其他技术。

4. 发明授权

US09729360B2 Method and apparatus for processing bit-interleaved data traffic in a communication network 有权
公开(公告)号：US09729360B2
公开(公告)日：2017-08-08
申请号：US13853754
申请日：2013-03-29
申请人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
发明人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
IPC分类号： H04L25/03 , H04L1/00
CPC分类号： H04L25/03866 , H04L1/0071
摘要： A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.

5. 发明授权

US08712243B2 Methods and apparatus for achieving multiple bit rates in passive optical networks 有权
标题翻译：在无源光网络中实现多个比特率的方法和装置
公开(公告)号：US08712243B2
公开(公告)日：2014-04-29
申请号：US11015152
申请日：2004-12-17
申请人： Hungkei Keith Chow , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
发明人： Hungkei Keith Chow , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： H04J14/08 , H04B10/00
CPC分类号： H04J3/1694 , H04L7/033
摘要： Systems and techniques for multiple bit rate optical data transmission. A passive optical network includes an optical line termination unit (OLT) connected to one or more optical network units (ONUs) by optical elements. The OLT is capable of performing downstream transmission to the ONUs at each of a variety of different bit rates, and each ONU performs upstream transmission at one or more bit rates. The OLT can sense a bit rate of a received transmission and change its operation so as to receive and process the transmission exhibiting the sensed bit rate. Each of the ONUs receives and processes downstream transmissions at one or more bit rates, but each ONU is capable of maintaining a phase and frequency lock to downstream transmissions at all bit rates supported by the OLT. One or more of the ONUs may also receive and process downstream transmissions exhibiting different or changed bit rates.
摘要翻译：用于多比特率光数据传输的系统和技术。无源光网络包括通过光学元件连接到一个或多个光网络单元（ONU）的光线路终端单元（OLT）。 OLT能够以各种不同比特率的每一个对ONU执行下行传输，并且每个ONU以一个或多个比特率执行上行传输。 OLT可以感测接收到的传输的比特率并改变其操作，以便接收和处理呈现感测到的比特率的传输。每个ONU以一个或多个比特速率接收和处理下游传输，但是每个ONU能够在由OLT支持的所有比特率下维持到下行传输的相位和频率锁定。一个或多个ONU还可以接收和处理呈现不同或改变的比特率的下行传输。

6. 发明授权

US07123675B2 Clock, data and time recovery using bit-resolved timing registers 有权
标题翻译：使用位解析定时寄存器的时钟，数据和时间恢复
公开(公告)号：US07123675B2
公开(公告)日：2006-10-17
申请号：US10255008
申请日：2002-09-25
申请人： Glenn M Boles , Alfred Earl Dunlop , Ilija Hadzic , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
发明人： Glenn M Boles , Alfred Earl Dunlop , Ilija Hadzic , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： H04L7/00
CPC分类号： H04J3/1694 , H04J3/0682 , H04L7/042
摘要： A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.
摘要翻译：公开了一种时钟恢复方法，其中数据字的FIFO延迟和数据字与接收机时钟之间的相位差用于对发射机进行数据传输。数据字和接收器时钟之间的相位差由字相对于存储缓冲器中的期望位置的偏移量确定。通过测量FIFO中的读指针和写指针之间的差来确定FIFO延迟，或者通过计算数据字进入FIFO的时间与当前时间的时间戳之间的差，从FIFO读取。

7. 发明授权

US07525971B2 Software-hardware partitioning of a scheduled medium-access protocol 有权
标题翻译：计划的媒体访问协议的软硬件分区
公开(公告)号：US07525971B2
公开(公告)日：2009-04-28
申请号：US11081932
申请日：2005-03-16
申请人： Martin D. Carroll , Ilija Hadzic , Dusan Suvakovic
发明人： Martin D. Carroll , Ilija Hadzic , Dusan Suvakovic
IPC分类号： H04L12/28 , H04J14/00
CPC分类号： H04L12/66 , H04L47/24
摘要： A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.
摘要翻译：一种被配置为在通信系统中实现调度介质访问协议（SMAP）的至少一部分的处理设备，包括处理器，耦合到处理器的存储器以及一个或多个附加硬件模块。在处理设备中实现的SMAP的部分的功能在存储在存储器中并且可由处理器执行的软件以及包括一个或多个附加硬件模块的硬件之间进行分区。在说明性实施例中，处理设备包括无源光网络的头端设备，并且功能性至少包括调度器和授权生成器，其中调度器在软件中实现，并且授权生成器被实现在硬件中。

8. 发明授权

US07242739B2 Method and apparatus for multiphase, fast-locking clock and data recovery 有权
标题翻译：用于多相，快速锁定时钟和数据恢复的方法和装置
公开(公告)号：US07242739B2
公开(公告)日：2007-07-10
申请号：US10460572
申请日：2003-06-12
申请人： Glenn M Boles , Alfred Earl Dunlop , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
发明人： Glenn M Boles , Alfred Earl Dunlop , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： H03D3/24
CPC分类号： H04L7/0338 , H04L7/042
摘要： A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.
摘要翻译：公开了一种在突发模式系统中有利的用于时钟和数据恢复的方法和装置。该时钟和数据恢复方法允许a）快速锁定到传输时钟的快速变化的相位，以及b）稳定跟踪传输时钟的缓慢变化的相位。这种快速锁定使连续传输突发之间的“保护带”最小化，而稳定跟踪提供可靠的数据跟踪，导致带宽的有效使用。产生多个时钟信号，每个具有不同的相位。确定输入信号数据流的相位，并且选择与输入数据流的相位相对应的多个中的期望时钟信号，并将其用于采样输入信号数据流。

9. 发明授权

US08326152B2 System and method for scheduling timeslots for transmission by optical nodes in an optical network 有权
标题翻译：用于调度光网络中光节点传输的时隙的系统和方法
公开(公告)号：US08326152B2
公开(公告)日：2012-12-04
申请号：US12760870
申请日：2010-04-15
申请人： Doutje T. Van Veen , Adriaan J. De Lind Van Wijngaarden , Dusan Suvakovic
发明人： Doutje T. Van Veen , Adriaan J. De Lind Van Wijngaarden , Dusan Suvakovic
IPC分类号： H04B10/00 , H04B10/08 , H04J14/00 , H04J14/02
CPC分类号： H04J14/02 , H04B10/07955 , H04J3/1694
摘要： A signal strength corresponding to an incoming optical burst from each of a plurality of optical nodes is measured. The measurements can be performed at system start-up, configuration/installation of the optical nodes and/or at certain intervals of operation of the optical nodes. Signal strength information for the optical nodes based on the measurements is stored in memory. When scheduling the optical nodes for transmission, a preferred transmission order is determined in response to the stored signal strength information. In an embodiment, the preferred order is determined to reduce differences in signal strength levels between consecutive optical bursts.
摘要翻译：测量与来自多个光学节点中的每一个的输入光脉冲串对应的信号强度。可以在系统启动，光节点的配置/安装和/或在光节点的特定操作间隔期间进行测量。基于测量的光节点的信号强度信息被存储在存储器中。当调度用于传输的光节点时，响应于所存储的信号强度信息来确定优选传输顺序。在一个实施例中，确定优选顺序以减少连续的光脉冲串之间的信号强度电平的差异。

10. 发明申请

US20060222129A1 High-speed serial transceiver with sub-nominal rate operating mode 有权
标题翻译：具有次标称速率操作模式的高速串行收发器
公开(公告)号：US20060222129A1
公开(公告)日：2006-10-05
申请号：US11093638
申请日：2005-03-30
申请人： Ilija Hadzic , Dusan Suvakovic
发明人： Ilija Hadzic , Dusan Suvakovic
IPC分类号： H04L7/00 , H04L7/02
CPC分类号： H04L7/0338
摘要： A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.
摘要翻译：通信设备包括接收机和数据恢复模块。接收器可以是串行收发器的一个元件，嵌入在FPGA或其他类型的可重新配置硬件中或以其他方式与FPGA或其他类型的可重新配置的硬件相关联。接收器可以用解锁的采样时钟操作。数据恢复模块被配置为检测由接收机使用解锁的采样时钟产生的数据信号样本中的转换边缘，并且从检测到的边缘确定用于恢复关联数据的采样点。数据恢复模块还被配置为在存在可归因于解锁的采样时钟的过渡边缘变化（例如一个或多个异常条件）的情况下，在采样点中提供调整。

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