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1. 发明授权

US5768542A Method and apparatus for automatically configuring circuit cards in a computer system 失效
公开(公告)号：US5768542A
公开(公告)日：1998-06-16
申请号：US774998
申请日：1996-12-27
申请人： Mark R. Enstrom , Ralph L. Lipe , David W. Voth , Robert T. Short , Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi
发明人： Mark R. Enstrom , Ralph L. Lipe , David W. Voth , Robert T. Short , Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi
IPC分类号： G06F13/40 , G06F13/12 , G06F13/14
CPC分类号： G06F13/4072
摘要： A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.

2. 发明授权

US5881252A Method and apparatus for automatically configuring circuit cards in a computer system 失效
标题翻译：在计算机系统中自动配置电路卡的方法和装置
公开(公告)号：US5881252A
公开(公告)日：1999-03-09
申请号：US920503
申请日：1997-08-29
申请人： Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi , Mark R. Enstrom , Ralph A. Lipe , David W. Voth , Robert T. Short
发明人： Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi , Mark R. Enstrom , Ralph A. Lipe , David W. Voth , Robert T. Short
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4072
摘要： A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.
摘要翻译：一种用于自动配置在计算机系统中使用的电路卡的方法和装置。本发明包括一种方法和装置，其能够在系统引导期间自动配置电路卡，而无需用户干预。本发明还包括一种用于计算机系统软件检测由电路卡请求的资源以便解决任何系统资源冲突的方法。

3. 发明授权

US5694555A Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets 失效
标题翻译：用于使用通信分组通过分层串行总线组件交换数据，状态和命令的方法和装置
公开(公告)号：US5694555A
公开(公告)日：1997-12-02
申请号：US619863
申请日：1996-03-19
申请人： Jeff Charles Morriss , Shaun Knoll , Puthiya Kottal Nizar , Richard M. Haslam , Ajay V. Bhatt , Sudarshan Bala Cadambi
发明人： Jeff Charles Morriss , Shaun Knoll , Puthiya Kottal Nizar , Richard M. Haslam , Ajay V. Bhatt , Sudarshan Bala Cadambi
IPC分类号： G06F13/36 , G06F13/00 , G06F13/38 , G06F13/42 , H04L12/40 , H04L12/64
CPC分类号： H04L12/40058 , G06F13/385 , G06F13/4291 , H04L12/40071 , H04L12/40117 , H04L12/40123
摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.
摘要翻译：电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。数据通信事务使用元素数据包进行，并根据事务协议进行。在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。连接管理事务以与数据通信事务相同的方式进行。

4. 发明授权

US5742847A M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions 失效
标题翻译：用于动态生成和维护用于轮询等时和异步功能的基于帧的轮询时间表的并购，其保证等时功能的延迟和带宽
公开(公告)号：US5742847A
公开(公告)日：1998-04-21
申请号：US331727
申请日：1994-10-31
申请人： Shaun Knoll , Jeff Charles Morriss , Ajay V. Bhatt , Puthiya Kottal Nizar , Richard M. Haslam , Sudarshan Bala Cadambi
发明人： Shaun Knoll , Jeff Charles Morriss , Ajay V. Bhatt , Puthiya Kottal Nizar , Richard M. Haslam , Sudarshan Bala Cadambi
IPC分类号： G06F13/10 , G06F13/22 , G06F13/40 , H04L12/40 , H04L12/64 , G06F13/14 , G06F13/20
CPC分类号： H04L12/40058 , G06F13/10 , G06F13/22 , G06F13/4022 , H04L12/40065
摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.
摘要翻译：电路和互补逻辑提供给总线控制器，多个1：n总线信号分配器，以及用于总线控制器的分级串行总线组件的多个总线接口，用于动态生成并维护基于帧的轮询时间表，以轮询总线代理连接到串行总线组件和串行总线元件本身的功能。分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。串行总线元件的这些电路和互补逻辑支持总线控制器收集各种关键操作特性。提供给总线控制器的电路和逻辑依次产生基于帧的轮询调度，这些收集的关键操作特性，保证等时外设的同步功能的延迟和带宽。在某些实施例中，响应于串行总线元件的实时连接/分离，提供给总线控制器的电路和逻辑进一步适应实时地基于其基于帧的轮询调度。

5. 发明授权

US5909556A M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets 失效
标题翻译：通过分层串行总线组合使用通信包交换日期，状态和命令的并购
公开(公告)号：US5909556A
公开(公告)日：1999-06-01
申请号：US980507
申请日：1997-12-01
申请人： Jeff Charles Morriss , Shaun Knoll , Puthiya Kottal Nizar , Richard M. Haslam , Ajay V. Bhatt , Sudarshan Bala Cadambi
发明人： Jeff Charles Morriss , Shaun Knoll , Puthiya Kottal Nizar , Richard M. Haslam , Ajay V. Bhatt , Sudarshan Bala Cadambi
IPC分类号： G06F13/36 , G06F13/00 , G06F13/38 , G06F13/42 , H04L12/40 , H04L12/64
CPC分类号： H04L12/40058 , G06F13/385 , G06F13/4291 , H04L12/40071 , H04L12/40117 , H04L12/40123
摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.
摘要翻译：电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。数据通信事务使用元素数据包进行，并根据事务协议进行。在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。连接管理事务以与数据通信事务相同的方式进行。

6. 发明授权

US07633877B2 Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link 失效
标题翻译：满足多速度点对点链路调试和测试的依从性的方法和装置
公开(公告)号：US07633877B2
公开(公告)日：2009-12-15
申请号：US11283303
申请日：2005-11-18
申请人： Debendra Das Sharma , Ajay V. Bhatt , David S. Dunning
发明人： Debendra Das Sharma , Ajay V. Bhatt , David S. Dunning
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： A method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link. In one embodiment, the method includes the selection of a compliance speed for a point-to-point link from at least two link frequencies supported by the point-to-point link. Once the compliance speed is selected for the point-to-point link, the point-to-point link is caused to enter a compliance testing mode. During compliance testing mode, a controller of the point-to-point link sets a compliance speed of the point-to-point link to the selected compliance speed. Once a compliance speed is set, a transmitter of the point-to-point link transmits a compliance pattern at the selected compliance speed. In one embodiment, the transmission of the compliance pattern at the selected compliance speed is used to generate a worst case eye diagram to determine compliance of the point-to-point link to a link specification. Other embodiments are described and claimed.
摘要翻译：一种用于满足调试和测试多速点对点链路的符合性的方法和装置。在一个实施例中，该方法包括从点对点链路所支持的至少两个链路频率中选择点对点链路的遵从速度。一旦为点对点链路选择了合规性速度，点对点链路便进入合规性测试模式。在合规测试模式期间，点对点链路的控制器将点对点链路的合规速度设置为所选择的合规速度。一旦达到合规速度，点对点链路的发射机就以所选择的合规速度传输合规模式。在一个实施例中，以所选择的合规速度传输合规性模式用于生成最坏情况的眼图，以确定点对点链路对链路规范的顺从性。描述和要求保护其他实施例。

7. 发明授权

US08719547B2 Providing hardware support for shared virtual memory between local and remote physical memory 有权
标题翻译：为本地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US08719547B2
公开(公告)日：2014-05-06
申请号：US12562477
申请日：2009-09-18
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

8. 发明授权

US08700821B2 Unified multi-transport medium connector architecture 有权
标题翻译：统一的多传输媒体连接器架构
公开(公告)号：US08700821B2
公开(公告)日：2014-04-15
申请号：US12229453
申请日：2008-08-22
申请人： Prashant R. Chandra , Ajay V. Bhatt , Kevin Kahn , Steve McGowan
发明人： Prashant R. Chandra , Ajay V. Bhatt , Kevin Kahn , Steve McGowan
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , G06F13/42 , G01R31/08 , H04L12/28 , H04L12/56 , H04J3/16 , H04B10/20 , H04B10/00 , G02B6/12 , G02B6/36 , G02B6/38 , H01R13/44 , H01R33/945
CPC分类号： G06F13/122 , H04L45/62 , H04L47/2491 , H04Q11/0062 , H04Q11/0066
摘要： A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括路由器，用于在多个主机控制器与一个或多个外围设备之间传输数据分组。路由器可以从主机控制器接收数据包，并通过数据传输路径将数据包发送到外围设备。外围设备通过第一通用多传输介质（UMTM）连接器耦合到第一数据传输路径。连接器包括能够传送光信号内的第一数据分组的光耦合器和能够在电信号内传输第一数据分组的电耦合。

9. 发明申请

US20130132683A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132683A1
公开(公告)日：2013-05-23
申请号：US13713614
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

10. 发明授权

US07757020B2 Point-to-point link negotiation method and apparatus 有权
标题翻译：点到点链接协商方法和装置
公开(公告)号：US07757020B2
公开(公告)日：2010-07-13
申请号：US11169527
申请日：2005-06-29
申请人： Debendra Das Sharma , Ajay V. Bhatt
发明人： Debendra Das Sharma , Ajay V. Bhatt
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4278 , Y02D10/14 , Y02D10/151
摘要： Point-to-point links between devices are brought up at a slowest available speed, and a faster link speed is negotiated after reaching an operational state.
摘要翻译：设备之间的点对点链路以最慢的可用速度启动，并且在达到操作状态之后协商更快的链路速度。

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