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    • 8. 发明申请
    • System and method for improved software simulation using a plurality of simulator checkpoints
    • 使用多个模拟器检查点改进软件仿真的系统和方法
    • US20060155525A1
    • 2006-07-13
    • US11032182
    • 2005-01-10
    • Maximino AguilarPatrick BohrerJames Stafford
    • Maximino AguilarPatrick BohrerJames Stafford
    • G06F9/455
    • G06F17/5022
    • A system and method is provided to improve software simulation. A software emulator is used in conjunction with a hardware simulator. A special snapshot instruction is included in the software code that is emulated. When the snapshot instruction is encountered, values such as register, memory, and program stack values, are stored creating an initial snapshot. Code continues to be emulated and, when the next snapshot instruction is encountered, the values are written to create a second snapshot. The initial values are used to set an initial state in a hardware model that is simulated on a hardware simulator. The results of the hardware simulation are compared to the second snapshot to uncover software errors and/or hardware errors so that the software can be modified or the hardware design can be modified. Multiple sets of snapshots can be taken to analyze multiple sections of the software program.
    • 提供了一种系统和方法来改进软件仿真。 软件仿真器与硬件模拟器结合使用。 特殊快照指令包含在仿真的软件代码中。 当遇到快照指令时,存储诸如寄存器,存储器和程序堆栈值的值,创建初始快照。 代码继续被仿真,并且当遇到下一个快照指令时,这些值被写入以创建第二个快照。 初始值用于在硬件模拟器上模拟的硬件模型中设置初始状态。 将硬件仿真的结果与第二个快照进行比较,以发现软件错误和/或硬件错误,从而可以修改软件或修改硬件设计。 可以采用多组快照来分析软件程序的多个部分。
    • 10. 发明申请
    • Method and system for managing cache injection in a multiprocessor system
    • 在多处理器系统中管理缓存注入的方法和系统
    • US20060064518A1
    • 2006-03-23
    • US10948407
    • 2004-09-23
    • Patrick BohrerAhmed GheithPeter HochschildRamakrishnan RajamonyHazim ShafiBalaram Sinharoy
    • Patrick BohrerAhmed GheithPeter HochschildRamakrishnan RajamonyHazim ShafiBalaram Sinharoy
    • G06F13/28
    • G06F13/28
    • A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
    • 用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器(SMP)或非均匀存储器访问(NUMA)多处理器环境中的直接存储器访问传输相关联的处理时间。 该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器,从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。 可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。 或者或与目标处理器识别结合,中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。 在NUMA多处理器系统中,选择完成的处理器/目标存储器,以便可访问目标存储器到处理器和相关联的高速缓存。