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1. 发明申请

US20070109078A1 Tunable MMIC (monolithic microwave integrated circuit) waveguide resonators 有权
标题翻译：可调MMIC（单片微波集成电路）波导谐振器
公开(公告)号：US20070109078A1
公开(公告)日：2007-05-17
申请号：US11288049
申请日：2005-11-14
申请人： Mark Kintis , Flavia Fong , Thomas Wong , Xing Lan
发明人： Mark Kintis , Flavia Fong , Thomas Wong , Xing Lan
IPC分类号： H01P7/00
CPC分类号： H01P7/065
摘要： A ferroelectric loaded waveguide resonator capable of operation at microwave, millimeter-wave and higher frequencies and suitable for integration into a three-dimensional monolithic microwave integrated circuit (3D MMIC) is disclosed. The resonator includes a resonator cavity, which, in one form of the invention, is formed by two parallel metal layers and a metallized wall structure extending between the metal layers. The cavity is filled with dielectric material and includes a layer of ferroelectric material, which is used to control the resonant frequency by varying a voltage bias applied to the ferroelectric layer. The cavity includes a slot in one of the metal layers and a coupling strip formed adjacent to the slot to provide electromagnetic coupling to other components, such as a voltage controlled oscillator (VCO). The invention can also be applied to other multi-metal semiconductor or wafer level packaging technologies.
摘要翻译：公开了一种能够在微波，毫米波和更高频率下操作并且适合于集成到三维单片微波集成电路（3D MMIC）中的铁电负载波导谐振器。谐振器包括谐振器腔，其在本发明的一种形式中由两个平行的金属层和在金属层之间延伸的金属化壁结构形成。空腔填充有电介质材料，并且包括铁电材料层，其用于通过改变施加到铁电层的电压偏压来控制谐振频率。空腔包括在金属层中的一个中的槽和与槽相邻形成的耦合条，以提供与其它部件（例如压控振荡器（VCO））的电磁耦合。本发明也可应用于其他多金属半导体或晶圆级封装技术。

2. 发明申请

US20070069824A1 3D MMIC VCO and methods of making the same 有权
标题翻译： 3D MMIC VCO和制作方法相同
公开(公告)号：US20070069824A1
公开(公告)日：2007-03-29
申请号：US11236033
申请日：2005-09-27
申请人： Mark Kintis , Flavia Fong , Thomas Wong , Xing Lan
发明人： Mark Kintis , Flavia Fong , Thomas Wong , Xing Lan
IPC分类号： H03K3/03
CPC分类号： H03B5/1841
摘要： A three dimensional (3D) microwave monolithic integrated circuit (MMIC) multi-push voltage controlled oscillator (VCO) and methods of making the same is provided. The 3D MMIC multi-push oscillator includes a plurality of matching frequency oscillators coupled to a phasing ring in substantially equidistantly spaced apart locations. A combined VCO output signal is provided at a central output connection point of the phasing ring. The central output connection point resides on a first plane. An output conductor transition has a first end coupled to the central output connection point and a second end provided as an output to the quad-push VCO. The output conductor transition extends transverse to the first plane and terminates at a second plane separated from the first plane. The multi-push oscillator can be a push-push, quad-push or N-push type VCO based on a particular implementation.
摘要翻译：提供三维（3D）微波单片集成电路（MMIC）多压电压控振荡器（VCO）及其制作方法。 3D MMIC多按钮振荡器包括多个匹配的频率振荡器，其耦合到基本上等间隔开的位置的相控环。在相控环的中心输出连接点处提供组合的VCO输出信号。中央输出连接点位于第一平面上。输出导体跃迁具有耦合到中心输出连接点的第一端和作为四推压VCO的输出提供的第二端。输出导体跃迁横向于第一平面延伸并终止于与第一平面分离的第二平面。多按钮振荡器可以是基于特定实现的推挽式，四推式或N推式VCO。

3. 发明申请

US20070052491A1 3D MMIC balun and methods of making the same 有权
标题翻译： 3D MMIC平衡 - 不平衡变换器及其制作方法
公开(公告)号：US20070052491A1
公开(公告)日：2007-03-08
申请号：US11218968
申请日：2005-09-02
申请人： Mark Kintis , Flavia Fong , Xing Lan
发明人： Mark Kintis , Flavia Fong , Xing Lan
IPC分类号： H03H7/42
CPC分类号： H01P5/10 , H01F17/0006 , H01F2021/125 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A three dimensional (3D) monolithic integrated circuit (MMIC) balun and methods of making the same are provided. A primary spiral winding is spaced apart from a secondary primary winding by a gap in a substantially aligned stacked configuration forming a balun. The gap medium can be a low dielectric constant material if employing a multi-metal process or air if employing a wafer level packaging process.
摘要翻译：提供了三维（3D）单片集成电路（MMIC）平衡 - 不平衡变换器及其制造方法。初级螺旋绕组与次级初级绕组间隔开一个形成一个平衡 - 不平衡变换器的基本对齐的堆叠结构的间隙。如果使用多金属工艺或空气，如果采用晶片级封装工艺，间隙介质可以是低介电常数材料。

4. 发明申请

US20070008048A1 Simple time domain pulse generator 有权
标题翻译：简单的时域脉冲发生器
公开(公告)号：US20070008048A1
公开(公告)日：2007-01-11
申请号：US11176029
申请日：2005-07-06
申请人： Mark Kintis , Flavia Fong
发明人： Mark Kintis , Flavia Fong
IPC分类号： H04B3/04
CPC分类号： H03K5/12 , H03K5/06 , H03K5/156
摘要： A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.
摘要翻译：脉冲发生电路和相关方法，用于产生用于雷达，高速采样，脉冲无线电和其他应用的单片微波集成电路（MMIC）中的极窄脉冲。正弦输入信号被提供给两个非线性冲击波发生器，它们被相反地偏置以产生彼此是镜像的周期性输出，一个具有非常陡峭的上升沿，一个具有非常陡峭的下降沿。组合的输出将完全相互抵消，但是在其中一个中引入轻微的时间延迟，这导致组合信号中的峰值较小。

5. 发明申请

US20060158277A1 Tunable, maximum power output, frequency harmonic comb generator 有权
标题翻译：可调谐，最大功率输出，频率谐波梳发生器
公开(公告)号：US20060158277A1
公开(公告)日：2006-07-20
申请号：US11038354
申请日：2005-01-19
申请人： Eric Mrozek , Flavia Fong , Mark Kintis
发明人： Eric Mrozek , Flavia Fong , Mark Kintis
IPC分类号： H04B3/04
CPC分类号： H03K5/12 , H03B25/00
摘要： A comb frequency generator that is tunable to vary the width of the pulses in the output signal and achieve a maximum power output at different harmonic frequencies. A wavefront compression device receives a sinusoidal input signal and provides wavefront compression to create a compressed signal having a series of periodic fast edges. A delay device receives the fast-edge compressed signal and delays the fast-edge signal to create a delayed fast-edge signal. A combining device receives the original fast-edge compressed signal and the delayed fast-edge compressed signal to generate an output signal including a series of pulses having a width determined by the delay of the delayed signal. In one embodiment, the delay device is a shorted transmission line stub having a length selectively set by a series of MEM devices. In another embodiment, the delay device is an NLTL variable time delay device that delays the fast-edge signal.
摘要翻译：梳状频率发生器，可调谐以改变输出信号中的脉冲宽度，并实现不同谐波频率下的最大功率输出。波前压缩装置接收正弦输入信号并提供波前压缩以产生具有一系列周期性快速边缘的压缩信号。延迟装置接收快速边缘压缩信号并延迟快速边缘信号以产生延迟的快速边缘信号。组合装置接收原始快速边缘压缩信号和延迟的快速边缘压缩信号，以产生包括具有由延迟信号的延迟确定的宽度的一系列脉冲的输出信号。在一个实施例中，延迟装置是具有由一系列MEM装置选择性地设置的长度的短路传输线短截线。在另一个实施例中，延迟装置是延迟快速边缘信号的NLTL可变时间延迟装置。

6. 发明申请

US20080169846A1 High efficiency NLTL comb generator using time domain waveform synthesis technique 有权
公开(公告)号：US20080169846A1
公开(公告)日：2008-07-17
申请号：US11651989
申请日：2007-01-11
申请人： Xing Lan , Mark Kintis , Flavia S. Fong
发明人： Xing Lan , Mark Kintis , Flavia S. Fong
IPC分类号： H03B21/00 , G06F1/04 , H03K7/02
CPC分类号： H03B25/00 , H03K5/12
摘要： A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.

7. 发明授权

US08610515B2 True time delay circuits including archimedean spiral delay lines 有权
标题翻译：真正的延时电路，包括阿基米德螺旋延迟线
公开(公告)号：US08610515B2
公开(公告)日：2013-12-17
申请号：US13103634
申请日：2011-05-09
申请人： Xing Lan , Mark Kintis , Chad Hansen
发明人： Xing Lan , Mark Kintis , Chad Hansen
IPC分类号： H01P1/18
CPC分类号： H01P9/02
摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.
摘要翻译：一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

8. 发明申请

US20120286899A1 ULTRA WIDEBAND TRUE TIME DELAY LINES 有权
标题翻译：超级宽带真正的延时线
公开(公告)号：US20120286899A1
公开(公告)日：2012-11-15
申请号：US13103634
申请日：2011-05-09
申请人： Xing Lan , Mark Kintis , Chad Hansen
发明人： Xing Lan , Mark Kintis , Chad Hansen
IPC分类号： H01P1/18
CPC分类号： H01P9/02
摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.
摘要翻译：一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

9. 发明授权

US07733194B2 Nonlinear transmission line modulator 有权
标题翻译：非线性传输线调制器
公开(公告)号：US07733194B2
公开(公告)日：2010-06-08
申请号：US11934310
申请日：2007-11-02
申请人： Xing Lan , Mark Kintis , Flavia S. Fong
发明人： Xing Lan , Mark Kintis , Flavia S. Fong
IPC分类号： H04B3/04
CPC分类号： H04L25/4902 , H04B1/71635 , H04B1/7174
摘要： A modulator is provided that comprises a nonlinear transmission line (NLTL) that is bias modulated by a baseband signal. A given logic state of the baseband signal determines a delay amount of a first carrier signal through the NLTL. The modulator further comprises an impulse forming network (IFN) that includes a first NLTL that receives the first carrier signal delayed by the determined delay amount and a second NLTL that receives a second carrier signal having a fixed delay amount. The first NLTL and second NLTL within the IFN have opposite diode polarity configurations. The modulator further comprises a power combiner that converts a delta delay of the first carrier signal relative to the second carrier signal to a sharp impulse that represents the given logic state of the baseband signal.
摘要翻译：提供了一种包括被基带信号偏置调制的非线性传输线（NLTL）的调制器。基带信号的给定逻辑状态确定通过NLTL的第一载波信号的延迟量。调制器还包括脉冲形成网络（IFN），其包括接收延迟了所确定的延迟量的第一载波信号的第一NLTL和接收具有固定延迟量的第二载波信号的第二NLTL。 IFN中的第一个NLTL和第二个NLTL具有相反的二极管极性配置。调制器还包括功率组合器，其将第一载波信号相对于第二载波信号的增量延迟转换为表示基带信号的给定逻辑状态的尖锐脉冲。

10. 发明授权

US07462956B2 High efficiency NLTL comb generator using time domain waveform synthesis technique 有权
标题翻译：高效率NLTL梳状发生器采用时域波形合成技术
公开(公告)号：US07462956B2
公开(公告)日：2008-12-09
申请号：US11651989
申请日：2007-01-11
申请人： Xing Lan , Mark Kintis , Flavia S. Fong
发明人： Xing Lan , Mark Kintis , Flavia S. Fong
IPC分类号： H03K3/64 , H03K5/06 , H03K5/12
CPC分类号： H03B25/00 , H03K5/12
摘要： A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.
摘要翻译：公开了一种用于合成具有脉冲段的波形的装置和方法。示例性发生器可以包括具有时间延迟元件的单元和产生脉冲段的脉冲发生器。输入分频器将输入信号分成通过单元传播的信号实例，输出组合器组合脉冲段以形成波形。脉冲发生器包括用于锐化脉冲段的上升沿和下降沿的锐化电路。锐化电路包括耦合到非线性传输线（NLTL）的可调谐延迟元件。另一个NLTL可以与可调谐延迟元件和第一个NLTL并联耦合。 NLTL包括耦合到肖特基二极管元件的阳极或阴极的输入部分，并且相应的阴极或阳极耦合到信号地。

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