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1. 发明授权

US5873512A Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier 失效
标题翻译：应用低温冶金膏形成粘结结构，将电子元件附着在载体上
公开(公告)号：US5873512A
公开(公告)日：1999-02-23
申请号：US847940
申请日：1997-04-25
申请人： James Daniel Bielick , Mark Kenneth Hoffmeyer , Phillip Duane Isaacs , Thomas Donald Kidd , David Allen Sluzewski
发明人： James Daniel Bielick , Mark Kenneth Hoffmeyer , Phillip Duane Isaacs , Thomas Donald Kidd , David Allen Sluzewski
IPC分类号： H01L21/60 , H05K3/12 , H05K3/34
CPC分类号： H01L24/83 , H01L24/31 , H05K3/3484 , H01L2224/11332 , H01L2224/13611 , H01L2224/29111 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01042 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0781 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/157 , H05K2201/035 , H05K2201/10734 , H05K2201/10984 , H05K2201/10992 , H05K2203/0338 , H05K2203/043 , H05K2203/0557 , H05K3/1216
摘要： A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.
摘要翻译：公开了一种形成用于集成电路和半导体电子器件和载体组件的接合结构的方法。冶金膏通过模板丝网印刷，并在回流过程中将模板留在原位。键合结构和冶金膏的熔点低于电子部件上的互连件的熔点，并且小于电子部件粘合到的载体组件的分解温度。

2. 发明授权

US06076726A Pad-on-via assembly technique 失效
标题翻译： Pad-on-via装配技术
公开(公告)号：US06076726A
公开(公告)日：2000-06-20
申请号：US108482
申请日：1998-07-01
申请人： Mark Kenneth Hoffmeyer , Phillip Duane Isaacs
发明人： Mark Kenneth Hoffmeyer , Phillip Duane Isaacs
IPC分类号： B23K1/00 , H01R12/04 , H05K3/34 , B23K31/02
CPC分类号： H05K3/3436 , B23K1/0016 , H05K3/3463 , B23K2201/42 , H05K2201/09481 , H05K2201/09572 , H05K2201/10992 , H05K2201/2081 , H05K2203/043 , H05K2203/0455 , H05K3/3452 , H05K3/3484 , Y02P70/613
摘要： Fine pitch area array packaging is achieved using a via-in-pad design within the area array attach portion of a printed circuit board (PCB). The limitation of the design is the wicking action, whereby solder applied to the capture pad contact surface is depleted by capillary action into the via hole when reflowed, causing insufficient solder to be present at the contact surface to effect reliable and repeatable electrical connections. In one implementation, an initial application of solder is applied to plug the via hole with a material having a higher final melting temperature than eutectic solder, thereby providing a stable plug. This plug is formed by the initial solder application that may be either a eutectic solder containing a third metal that forms intermetallic compounds, when reflowed, that elevate the liquidus temperature or a solder having a different formulation with an inherent higher melting temperature. An alternative implementation is to plate the via hole with a material, such as nickel, which prevents eutectic solder, applied to the via capture pad contact surface, from wetting the hole surface and being drawn away from the contact surface by capillary action. Thus, the solder, applied to the via capture pad and used to establish an electrical connection is not depleted.
摘要翻译：使用在印刷电路板（PCB）的区域阵列附着部分内的通孔焊盘设计实现细间距区域阵列封装。设计的限制是芯吸作用，由此当回流时，施加到捕获垫接触表面的焊料被毛细管作用通入通孔中，导致在接触表面处存在不足的焊料以实现可靠和可重复的电连接。在一个实施方案中，施加焊料的初始应用以用比共晶焊料更高的最终熔融温度的材料堵塞通孔，从而提供稳定的插塞。该插头由初始焊料应用形成，其可以是包含形成金属间化合物的第三金属的共晶焊料，当回流时，提高液相线温度的焊料或具有固有的较高熔融温度的不同配方的焊料。另一种实施方案是用诸如镍的材料对通孔进行平板化，其防止施加到通孔捕获垫接触表面的共晶焊料润湿孔表面并通过毛细管作用从接触表面拉出。因此，施加到通孔捕获垫并用于建立电连接的焊料不会耗尽。

3. 发明授权

US06300578B1 Pad-on-via assembly technique 有权
标题翻译： Pad-on-via装配技术
公开(公告)号：US06300578B1
公开(公告)日：2001-10-09
申请号：US09512131
申请日：2000-02-24
申请人： Mark Kenneth Hoffmeyer , Phillip Duane Isaacs
发明人： Mark Kenneth Hoffmeyer , Phillip Duane Isaacs
IPC分类号： H01R1204
CPC分类号： H05K3/3436 , B23K1/0016 , B23K2101/42 , H05K3/3452 , H05K3/3463 , H05K3/3484 , H05K2201/09481 , H05K2201/09572 , H05K2201/10992 , H05K2201/2081 , H05K2203/043 , H05K2203/0455 , Y02P70/613
摘要： Fine pitch area array packaging is achieved using a via-in-pad design within the area array attach portion of a printed circuit board (PCB). The limitation of the design is the wicking action, whereby solder applied to the capture pad contact surface is depleted by capillary action into the via hole when reflowed, causing insufficient solder to be present at the contact surface to effect reliable and repeatable electrical connections. In one implementation, an initial application of solder is applied to plug the via hole with a material having a higher final melting temperature than eutectic solder, thereby providing a stable plug. This plug is formed by the initial solder application that may be either a eutectic solder containing a third metal that forms intermetallic compounds, when reflowed, that elevate the liquidus temperature or a solder having a different formulation with an inherent higher melting temperature. An alternative implementation is to plate the via hole with a material, such as nickel, which prevents eutectic solder, applied to the via capture pad contact surface, from wetting the hole surface and being drawn away from the contact surface by capillary action. Thus, the solder, applied to the via capture pad and used to establish an electrical connection is not depleted.
摘要翻译：使用在印刷电路板（PCB）的区域阵列附着部分内的通孔焊盘设计实现细间距区域阵列封装。设计的限制是芯吸作用，由此当回流时，施加到捕获垫接触表面的焊料被毛细管作用通入通孔中，导致在接触表面处存在不足的焊料以实现可靠和可重复的电连接。在一个实施方案中，施加焊料的初始应用以用比共晶焊料更高的最终熔融温度的材料堵塞通孔，从而提供稳定的插塞。该插头由初始焊料应用形成，其可以是包含形成金属间化合物的第三金属的共晶焊料，当回流时，提高液相线温度的焊料或具有固有的较高熔融温度的不同配方的焊料。另一种实施方案是用诸如镍的材料对通孔进行平板化，其防止施加到通孔捕获垫接触表面的共晶焊料润湿孔表面并通过毛细管作用从接触表面拉出。因此，施加到通孔捕获垫并用于建立电连接的焊料不会耗尽。

4. 发明授权

US5806753A Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier 失效
公开(公告)号：US5806753A
公开(公告)日：1998-09-15
申请号：US577586
申请日：1995-12-22
申请人： James Daniel Bielick , Mark Kenneth Hoffmeyer , Phillip Duane Isaacs , Thomas Donald Kidd , David Allen Sluzewski
发明人： James Daniel Bielick , Mark Kenneth Hoffmeyer , Phillip Duane Isaacs , Thomas Donald Kidd , David Allen Sluzewski
IPC分类号： H01L21/60 , H05K3/12 , H05K3/34
CPC分类号： H01L24/83 , H01L24/31 , H05K3/3484 , H01L2224/11332 , H01L2224/13611 , H01L2224/29111 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01042 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0781 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/157 , H05K2201/035 , H05K2201/10734 , H05K2201/10984 , H05K2201/10992 , H05K2203/0338 , H05K2203/043 , H05K2203/0557 , H05K3/1216
摘要： A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.

5. 发明授权

US5789930A Apparatus and method to test for known good die 失效
标题翻译：测试已知好的模具的装置和方法
公开(公告)号：US5789930A
公开(公告)日：1998-08-04
申请号：US572591
申请日：1995-12-14
申请人： Phillip Duane Isaacs , David Allen Sluzewski , Mark Kenneth Hoffmeyer
发明人： Phillip Duane Isaacs , David Allen Sluzewski , Mark Kenneth Hoffmeyer
IPC分类号： G01R31/28 , H05K3/34 , G01R31/02
CPC分类号： H05K3/3436 , G01R31/2886 , H05K2201/035 , H05K2203/162 , H05K3/3484 , Y02P70/613
摘要： The present invention may be characterized as an improved integrated circuit die testing system which includes a number of components which cooperate together. An integrated circuit carrier is provided for holding the integrated circuit die. Attached to the integrated circuit carrier is a chip site. Proximate to this chip site exists a plurality of contact pads. These contact pads are electrically coupled to a plurality of test points. Also provided is an integrated circuit die. Finally, a pattern of electrically conductive paste is provided. This electrically conductive paste electrically couples the integrated circuit die and the contact pads thereby allowing the integrated circuit die to be tested from the test points.
摘要翻译：本发明可以被表征为一种改进的集成电路芯片测试系统，其包括多个组合在一起的组件。提供了用于保持集成电路管芯的集成电路载体。连接到集成电路的载体是一个芯片现场。靠近该芯片位置存在多个接触垫。这些接触垫电耦合到多个测试点。还提供集成电路管芯。最后，提供导电浆料的图案。该导电浆料电耦合集成电路管芯和接触焊盘，从而允许从测试点测试集成电路管芯。

6. 发明授权

US08287336B2 Method of manufacturing a venting device for tamper resistant electronic modules 失效
标题翻译：制造防篡改电子模块通风装置的方法
公开(公告)号：US08287336B2
公开(公告)日：2012-10-16
申请号：US11686102
申请日：2007-03-14
申请人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
发明人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
IPC分类号： H05K5/00
CPC分类号： H05K5/0213 , H01L23/573 , H01L23/585 , H01L2924/0002 , H05K5/0208 , Y10T29/49885 , H01L2924/00
摘要： A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device consists of two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.
摘要翻译：用于电子电路的防篡改外壳包括内铜壳，围绕内壳缠绕的篡改感测网，包围内壳和篡改感测网的外铜壳，以及从内部内部形成通风通道的排气装置壳体到外壳外部，排气通道在篡改感测网的重叠层之间通过，并且沿其长度具有至少一个直角弯曲。排气装置由沿着其长度层压在一起的两条薄的聚酰胺覆盖层材料组成，并且一长度的羊毛纱线夹在两条薄条之间并从条的一端延伸到条的另一端以形成通风口渠道。纱线的长度遵循第一和第二条带之间的之字形路径，之字形路径包括至少一个直角弯曲部。

7. 发明申请

US20150007427A1 METHOD OF MANUFACTURING A VENTING DEVICE FOR TAMPER RESISTANT ELECTRONIC MODULES 有权
标题翻译：制造用于阻燃电子模块的通风装置的方法
公开(公告)号：US20150007427A1
公开(公告)日：2015-01-08
申请号：US13594937
申请日：2012-08-27
申请人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
发明人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
IPC分类号： H05K5/02
CPC分类号： H05K5/0213 , H01L23/573 , H01L23/585 , H01L2924/0002 , H05K5/0208 , Y10T29/49885 , H01L2924/00
摘要： A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device consists of two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.
摘要翻译：用于电子电路的防篡改外壳包括内铜壳，围绕内壳缠绕的篡改感测网，包围内壳和篡改感测网的外铜壳，以及从内部内部形成通风通道的排气装置壳体到外壳外部，排气通道在篡改感测网的重叠层之间通过，并且沿其长度具有至少一个直角弯曲。排气装置由沿着其长度层压在一起的两条薄的聚酰胺覆盖层材料组成，并且一长度的羊毛纱线夹在两条薄条之间并从条的一端延伸到条的另一端以形成通风口渠道。纱线的长度遵循第一和第二条带之间的之字形路径，之字形路径包括至少一个直角弯曲部。

8. 发明授权

US07214874B2 Venting device for tamper resistant electronic modules 失效
标题翻译：防篡改电子模块通风装置
公开(公告)号：US07214874B2
公开(公告)日：2007-05-08
申请号：US10981021
申请日：2004-11-04
申请人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
发明人： John Richard Dangler , Phillip Duane Isaacs , Arvind Kumar Sinha
IPC分类号： H02G3/08
CPC分类号： H05K5/0213 , H01L23/573 , H01L23/585 , H01L2924/0002 , H05K5/0208 , Y10T29/49885 , H01L2924/00
摘要： A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device includes two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.
摘要翻译：用于电子电路的防篡改外壳包括内铜壳，围绕内壳缠绕的篡改感测网，包围内壳和篡改感测网的外铜壳，以及从内部内部形成通风通道的排气装置壳体到外壳外部，排气通道在篡改感测网的重叠层之间通过，并且沿其长度具有至少一个直角弯曲。排气装置包括沿其长度层叠在一起的两条薄的聚酰胺覆盖层材料，以及夹在两条薄条之间的长度的羊毛，并且从带的一端延伸到带的另一端以形成排气通道。纱线的长度遵循第一和第二条带之间的之字形路径，之字形路径包括至少一个直角弯曲部。

9. 发明授权

US06572009B2 Passive and active heat retention device for solder fountain rework 失效
公开(公告)号：US06572009B2
公开(公告)日：2003-06-03
申请号：US10038930
申请日：2002-01-03
申请人： Scott Peter Graves , Phillip Duane Isaacs
发明人： Scott Peter Graves , Phillip Duane Isaacs
IPC分类号： B23K3706
CPC分类号： B23K3/085 , H05K3/225 , H05K3/3447 , H05K3/3452 , H05K3/3468 , H05K2203/0557
摘要： A method and apparatus for retaining heat at a pin-in-hole rework site on a printed circuit board during solder fountain rework of the board. A preheated heat retention plate is attached to the rework side of the printed circuit board. The heat retention plate covers a substantial portion of the board surface. During rework of the printed circuit board, the heat retention plate minimizes the temperature gradient between the rework site of the printed circuit board and the remainder of the printed circuit board. During the rework, the heat retention plate can be heated by an active heater in order to maintain a constant temperature gradient between the rework site of the board and the remainder of the board. By minimizing the escape of heat from the rework site, the number of solder cycles required to rework the board is decreased, resulting in reduced board rework times and increased board longevity.

10. 发明授权

US6127204A Column grid array or ball grid array pad on via 失效
标题翻译：柱格栅阵列或球栅阵列垫
公开(公告)号：US6127204A
公开(公告)日：2000-10-03
申请号：US111312
申请日：1998-07-07
申请人： Phillip Duane Isaacs , Miles Frank Swain , Connie Jean Mathison
发明人： Phillip Duane Isaacs , Miles Frank Swain , Connie Jean Mathison
IPC分类号： H05K1/11 , H05K3/34 , H05K3/42 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H05K3/3421 , H05K1/112 , H05K3/3436 , H05K2201/09472 , H05K2201/09827 , H05K2201/09845 , H05K2201/10734 , H05K2203/0415 , H05K2203/0455 , H05K3/429 , Y02P70/613
摘要： A electronic apparatus and a process for its manufacture are disclosed. The apparatus includes a planar card for accommodating an electronics module package having protruding solder columns and solder joints to mechanically mount and electrically connect the solder columns of the module to the planar card. The planar card includes a first side and a second side, a plurality of wiring lines forming a wiring pattern, and a plurality of vias extending at least partially through the card. Each of the vias includes at least one recessed area extending from one or both sides of the card. The recessed areas extending to a depth within the planar card sufficient to wick the solder joints, and the each of the recessed areas are shaped to provide surface tension to mechanically retain the solder joints.
摘要翻译：公开了一种电子设备及其制造方法。该装置包括用于容纳具有突出的焊料柱和焊点的电子模块封装的平面卡，以将模块的焊料柱机械地安装和电连接到平面卡。平面卡包括第一侧和第二侧，形成布线图形的多条布线和至少部分延伸穿过卡的多个通孔。每个通孔包括从卡的一侧或两侧延伸的至少一个凹陷区域。凹陷区域延伸到平面卡片内的深度以足以吸住焊接接头，并且每个凹陷区域被成形为提供表面张力以机械地保持焊接接头。

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