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1. 发明授权

US5686747A Integrated circuits comprising interconnecting plugs 失效
标题翻译：包括互连插头的集成电路
公开(公告)号：US5686747A
公开(公告)日：1997-11-11
申请号：US700320
申请日：1996-08-07
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108 , H01L29/41
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; e）有点线 f）位于所述位线和所述有效区域之间的介电绝缘层; g）延伸穿过绝缘层并将位线与另一有源区域电互连的位线插头，位线插头包括导电环形环。还公开了利用环形互连环的集成电路，超越了存储器件。还公开了具有另外的径向向内的绝缘环形环和导电环的这种结构。还公开了一种在具有这种环的存储器单元的电容器阵列上形成位线的方法。

2. 发明授权

US5821140A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
公开(公告)号：US5821140A
公开(公告)日：1998-10-13
申请号：US732067
申请日：1996-10-16
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

3. 发明授权

US5563089A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
标题翻译：在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列
公开(公告)号：US5563089A
公开(公告)日：1996-10-08
申请号：US394545
申请日：1995-02-22
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; e）有点线 f）位于所述位线和所述有效区域之间的介电绝缘层; g）延伸穿过绝缘层并将位线与另一有源区域电互连的位线插头，位线插头包括导电环形环。还公开了利用环形互连环的集成电路，超越了存储器件。还公开了具有另外的径向向内的绝缘环形环和导电环的这种结构。还公开了一种在具有这种环的存储器单元的电容器阵列上形成位线的方法。

4. 发明授权

US5962885A Method of forming a capacitor and a capacitor construction 失效
标题翻译：电容器结构
公开(公告)号：US5962885A
公开(公告)日：1999-10-05
申请号：US935966
申请日：1997-09-23
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.
摘要翻译：本发明包括电容器结构。一方面，本发明包括堆叠式电容器结构，其包括：a）衬底; b）设置在所述基底上的导电流道，所述流道具有外导电表面; c）邻近导电流道的衬底上的节点; d）与所述节点电连接的导电柱，所述柱相对于邻近导电流道的节点向外突出，所述柱具有外表面; e）与所述支柱电连接的导电存储节点容器层; f）电容器存储节点层上的电容器介电层; 和g）电容器介电层上的导电外电容器板; 以及h）所述柱外表面位于所述流道外表面的正上方。

5. 发明授权

US5789304A Method of forming a capacitor 失效
公开(公告)号：US5789304A
公开(公告)日：1998-08-04
申请号：US741832
申请日：1996-10-31
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.

6. 发明授权

US5604147A Method of forming a cylindrical container stacked capacitor 失效
标题翻译：形成圆柱形容器堆叠电容器的方法
公开(公告)号：US5604147A
公开(公告)日：1997-02-18
申请号：US440212
申请日：1995-05-12
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.
摘要翻译：形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间，支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻穿过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。还公开了这种电容器结构。

7. 发明授权

US6010941A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US6010941A
公开(公告)日：2000-01-04
申请号：US112629
申请日：1998-07-09
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.
摘要翻译：形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间，支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻通过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。还公开了这种电容器结构。

8. 发明申请

US20090315154A1 SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT 有权
标题翻译：具有通孔基板互连的半导体
公开(公告)号：US20090315154A1
公开(公告)日：2009-12-24
申请号：US12142251
申请日：2008-06-19
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L23/48 , H01L21/768 , H01L21/8234
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

9. 发明授权

US07601591B2 Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权
标题翻译：在存储器件上制造侧壁间隔物的方法，以及包括其的装置
公开(公告)号：US07601591B2
公开(公告)日：2009-10-13
申请号：US12020752
申请日：2008-01-28
申请人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

10. 发明申请

US20070218616A1 Semiconductor constructions, and methods of forming semiconductor constructions 有权
标题翻译：半导体结构以及形成半导体结构的方法
公开(公告)号：US20070218616A1
公开(公告)日：2007-09-20
申请号：US11377094
申请日：2006-03-16
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： H01L21/8234
CPC分类号： H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.
摘要翻译：本发明包括将部分SOI并入晶体管结构的方法。在特定方面，电介质材料设置在半导体材料上，并被图案化成由间隙分开的至少两个段。然后在电介质材料上并在间隙内生长附加的半导体材料。随后，形成晶体管以在附加半导体材料内包括源极/漏极区域，并且包括在源极/漏极区域之间的沟道。源极/漏极区域中的至少一个主要直接位于电介质材料的一段上，并且沟道不主要直接位于介电材料的任何部分上方。本发明还包括包括对应于电介质材料段的部分SOI的构造，以及主要直接位于介电材料段上的至少一个源/漏区的晶体管，以及不主要直接位于电介质材料的任何段上的沟道。

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