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1. 发明授权

US08933933B2 Optimizing a graphics rendering pipeline using early Z-mode 有权
标题翻译：使用早期Z模式优化图形渲染管道
公开(公告)号：US08933933B2
公开(公告)日：2015-01-13
申请号：US11430635
申请日：2006-05-08
申请人： Mark J. French , Emmett M. Kilgariff , Steven E. Molnar , Walter R. Steiner , Douglas A. Voorhies , Adam Clark Weitkemper
发明人： Mark J. French , Emmett M. Kilgariff , Steven E. Molnar , Walter R. Steiner , Douglas A. Voorhies , Adam Clark Weitkemper
IPC分类号： G06T15/40 , G06T15/00
CPC分类号： G06T15/405 , G06T15/005
摘要： One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.
摘要翻译：本发明的一个实施例阐述了在可能的情况下在像素着色之前推进Z检验操作的架构。由设置引擎维护的当前呈现状态确定是否可以在着色引擎之上前进Z检验功能以进行“早期”Z检验，或者Z检验功能是否应该延迟到“晚期”的阴影操作之后 “Z测试。数据在流水线中动态地路由到每个处理引擎，以便由当前呈现状态确定的早期Z或后期Z的适当数据流是动态构造的。早期Z和晚期Z配置都使用相同的功能单元。

2. 发明授权

US07023437B1 System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering 有权
标题翻译：用于在多遍渲染期间使用后几何数据流来加速图形处理的系统和方法
公开(公告)号：US07023437B1
公开(公告)日：2006-04-04
申请号：US10230124
申请日：2002-08-27
申请人： Douglas A. Voorhies , Edward C. Greene , Emmett M. Kilgariff , Svetoslav Tzvetkov
发明人： Douglas A. Voorhies , Edward C. Greene , Emmett M. Kilgariff , Svetoslav Tzvetkov
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A system and method are provided for accelerating graphics processing utilizing multiple-pass rendering. Initially, geometry operations are performed on graphics data, and the graphics data is stored in memory. During a first rendering pass, various operations take place. For example, the graphics data is read from the memory, and the graphics data is rasterized. Moreover, first z-culling operations are performed utilizing the graphics data. Such first z-culling operations maintain a first occlusion image. During a second rendering pass, the graphics data is read from memory. Still yet, the graphics data is rasterized and second z-culling operations are performed utilizing the graphics data and the first occlusion image. Moreover, visibility operations are performed utilizing the graphics data and a second occlusion image. Raster-processor operations are also performed utilizing the graphics data, during the second rendering pass.
摘要翻译：提供了一种利用多遍渲染加速图形处理的系统和方法。最初，对图形数据进行几何运算，图形数据存储在存储器中。在第一次渲染过程中，进行各种操作。例如，从存储器读取图形数据，并且图形数据被光栅化。此外，利用图形数据执行第一z淘选操作。这样的第一z-淘汰操作保持第一遮挡图像。在第二次渲染过程中，从存储器读取图形数据。仍然，图形数据被光栅化，并且使用图形数据和第一遮挡图像来执行第二z剔除操作。此外，利用图形数据和第二遮挡图像执行可视性操作。在第二次渲染过程中，还使用图形数据执行栅格处理器操作。

3. 发明申请

US20110090220A1 ORDER-PRESERVING DISTRIBUTED RASTERIZER 有权
标题翻译：订购保存分配的RASTERIZER
公开(公告)号：US20110090220A1
公开(公告)日：2011-04-21
申请号：US12580017
申请日：2009-10-15
申请人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
发明人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
IPC分类号： G06F15/80 , G06T15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
摘要翻译：本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。多个独立的几何单元在不同的图形基元上同时执行几何处理。原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

4. 发明授权

US08319783B1 Index-based zero-bandwidth clears 有权
标题翻译：基于索引的零带宽清除
公开(公告)号：US08319783B1
公开(公告)日：2012-11-27
申请号：US12340493
申请日：2008-12-19
申请人： David Kirk McAllister , Steven E. Molnar , Peter B. Holmqvist , Jerome F. Duluk, Jr. , Cass W. Everitt , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck
发明人： David Kirk McAllister , Steven E. Molnar , Peter B. Holmqvist , Jerome F. Duluk, Jr. , Cass W. Everitt , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck
IPC分类号： G06T1/60 , G09G5/39 , G09G5/36 , G09G5/37
CPC分类号： G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/122
摘要： A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.
摘要翻译：执行零带宽清除的系统和方法在执行清除和后续读取操作时减少图形处理器的外部存储器访问。一组清晰的值存储在图形处理器中。可以使用零带宽清除命令来配置颜色或z缓冲器的每个部分，以引用清除值而不写入外部存储器。当执行读取访问时，清除值被提供给请求者而不访问外部存储器。

5. 发明授权

US07508398B1 Transparent antialiased memory access 有权
标题翻译：透明抗锯齿存储器访问
公开(公告)号：US07508398B1
公开(公告)日：2009-03-24
申请号：US10646076
申请日：2003-08-22
申请人： John S. Montrym , Brian D. Hutsell , Steven E. Molnar , Gary M. Tarolli , Christopher T. Cheng , Emmett M. Kilgariff , Abraham B. de Waal
发明人： John S. Montrym , Brian D. Hutsell , Steven E. Molnar , Gary M. Tarolli , Christopher T. Cheng , Emmett M. Kilgariff , Abraham B. de Waal
IPC分类号： G06F12/10 , G09G5/36 , G09G5/00
CPC分类号： G06T1/60 , G09G5/363 , G09G5/393 , G09G2320/02 , G09G2340/10 , G09G2360/18
摘要： A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame buffer then the memory address is transformed into one or more physical addresses within a frame buffer that is utilized for antialiasing. The frame buffer may be a single memory space containing subpixel information corresponding to pixels of the virtual frame buffer. Subpixels located at the physical addresses within the frame buffer are then accessed. The disclosed invention provides for direct access by a software application.
摘要翻译：用于提供抗混叠存储器访问的系统和方法包括接收访问存储器地址的请求。检查存储器地址以确定存储器地址是否在虚拟帧缓冲器内。如果存储器地址在虚拟帧缓冲器内，则存储器地址被转换为用于抗锯齿的帧缓冲器内的一个或多个物理地址。帧缓冲器可以是包含对应于虚拟帧缓冲器的像素的子像素信息的单个存储器空间。然后访问位于帧缓冲器内的物理地址的子像素。所公开的发明提供了软件应用程序的直接访问。

6. 发明授权

US08587581B2 Order-preserving distributed rasterizer 有权
公开(公告)号：US08587581B2
公开(公告)日：2013-11-19
申请号：US12580017
申请日：2009-10-15
申请人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
发明人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
IPC分类号： G06T17/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

7. 发明授权

US08330766B1 Zero-bandwidth clears 有权
标题翻译：零带宽清除
公开(公告)号：US08330766B1
公开(公告)日：2012-12-11
申请号：US12340496
申请日：2008-12-19
申请人： David Kirk McAllister , Steven E. Molnar , Jerome F. Duluk, Jr. , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck , James Michael O'Connor , John Matthew Burgess , Gregory Alan Muthler , James Robertson
发明人： David Kirk McAllister , Steven E. Molnar , Jerome F. Duluk, Jr. , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck , James Michael O'Connor , John Matthew Burgess , Gregory Alan Muthler , James Robertson
IPC分类号： G09G5/36 , G06T15/40
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/122
摘要： A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each region of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.
摘要翻译：执行零带宽清除的系统和方法在执行清除和后续读取操作时减少图形处理器的外部存储器访问。一组清晰的值存储在图形处理器中。可以使用零带宽清除命令来配置颜色或z缓冲区的每个区域以引用清除值而不写入外部存储器。当执行读取访问时，清除值被提供给请求者而不访问外部存储器。

8. 发明授权

US08862823B1 Compression status caching 有权
标题翻译：压缩状态缓存
公开(公告)号：US08862823B1
公开(公告)日：2014-10-14
申请号：US12340503
申请日：2008-12-19
申请人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
发明人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/0848 , G06F12/1009 , G06F12/123 , G06F2212/1041 , G06F2212/401 , G06F2212/455 , G06F2212/466 , G06T1/60
摘要： One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.
摘要翻译：本发明的一个实施例提出了一种被配置为存储存储在外部存储器中的存储器块的压缩信息的压缩状态缓存。数据高速缓存单元被配置为基于存储在压缩状态位高速缓存中的压缩信息，响应于高速缓存未命中来请求来自外部存储器的压缩数据。活动缓冲区的压缩状态根据需要动态交换到压缩状态缓存。可以为活动缓冲区内的一个或多个瓦片指定不同的压缩格式。所公开的压缩状态高速缓存的一个优点是可以将大量附加存储器分配为可压缩存储器块，而不会引起相应的管芯区域成本，因为存储在附加存储器中的芯片外的存储器的一部分被缓存在压缩状态缓存。

9. 发明授权

US08704836B1 Distributing primitives to multiple rasterizers 有权
标题翻译：将原语分发到多个光栅化器
公开(公告)号：US08704836B1
公开(公告)日：2014-04-22
申请号：US12581700
申请日：2009-10-19
申请人： Johnny S. Rhoades , Steven E. Molnar , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
发明人： Johnny S. Rhoades , Steven E. Molnar , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
IPC分类号： G06F15/16
CPC分类号： G06T15/005 , G06T11/40 , G06T2210/12 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
摘要翻译：本发明的一个实施例提出了一种用于将原语并行分配到多个光栅化器的技术。多个独立的几何单元在不同的图形基元上同时执行几何处理。原始分配方案以每个时钟的多个基元的速率将原始图元从多个几何单元同时传送到多个光栅化器。多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

10. 发明申请

US20110090251A1 ALPHA-TO-COVERAGE VALUE DETERMINATION USING VIRTUAL SAMPLES 有权
标题翻译：使用虚拟样品的ALPHA到覆盖值确定
公开(公告)号：US20110090251A1
公开(公告)日：2011-04-21
申请号：US12904935
申请日：2010-10-14
申请人： Walter E. Donovan , Emmett M. Kilgariff , Steven E. Molnar , Christian Amsinck , Robert Ohannessian
发明人： Walter E. Donovan , Emmett M. Kilgariff , Steven E. Molnar , Christian Amsinck , Robert Ohannessian
IPC分类号： G09G5/00
CPC分类号： G06T15/503 , G06T15/005 , G09G5/363 , G09G5/393 , G09G2360/123
摘要： One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
摘要翻译：本发明的一个实施例提出了一种将α值转换为像素覆盖掩码的技术。在每个像素内的多个“实”样本位置采样几何覆盖。为这些实际样本中的每一个计算颜色和深度值。片段α值用于确定实际样本和附加“虚拟”样本的alpha覆盖掩码，其中掩码位中设置的位数与alpha值成比例。与仅使用真实样本相比，alpha到覆盖模式使用虚拟样本来增加每个像素的透明度级别数。 alpha到覆盖模式可以与虚拟覆盖抗锯齿一起使用，以提供用于渲染抗锯齿图像的更高质量的透明度。

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