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1. 发明授权

US08117392B2 Method and apparatus for efficient ordered stores over an interconnection network 有权
标题翻译：通过互连网络实现有效存储的方法和装置
公开(公告)号：US08117392B2
公开(公告)日：2012-02-14
申请号：US10691176
申请日：2003-10-22
申请人： Mark J. Charney , Ravi Rajwar , Pritpal S. Ahuja , Matthew C. Mattina
发明人： Mark J. Charney , Ravi Rajwar , Pritpal S. Ahuja , Matthew C. Mattina
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F12/0813 , G06Q30/0601
摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
摘要翻译：物理分布式高速缓冲存储器系统包括互连网络，第一级高速缓存存储器片和第二级高速缓存存储器片。第一级缓存存储器片耦合到互连网络以生成标记的有序存储请求。每个标记的有序存储请求都具有包括请求者标识和存储序列令牌的标签。第二级高速缓存存储器片耦合到互连网络，以响应于标记的有序存储请求的每个标签跨物理分布式高速缓冲存储器系统按顺序执行有序存储请求。

2. 发明授权

US06925552B2 Method and system with multiple exception handlers in a processor 失效
标题翻译：处理器中有多个异常处理程序的方法和系统
公开(公告)号：US06925552B2
公开(公告)日：2005-08-02
申请号：US09884675
申请日：2001-06-19
申请人： Matthew H. Reilly , Matthew C. Mattina , Shane L. Bell , Chuan-Hua Chang
发明人： Matthew H. Reilly , Matthew C. Mattina , Shane L. Bell , Chuan-Hua Chang
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3842
摘要： An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.
摘要翻译：处理器的异常处理程序分为两个功能单元，以允许将异常分为两类。第一类异常包括性能关键的除外指令，而第二类包括非性能关键的除外指令。性能关键异常被路由到推测性的异常处理程序，即异常指令可能位于程序流的推测路径中，该异常处理程序可以推测性地解析异常。非性能关键异常被路由到非推测性异常处理程序，该异常处理程序仅在排除的指令确定在程序流的实际路径中执行时才解析异常。

3. 发明授权

US07240186B2 System and method to avoid resource contention in the presence of exceptions 有权
标题翻译：在异常情况下避免资源争用的系统和方法
公开(公告)号：US07240186B2
公开(公告)日：2007-07-03
申请号：US09906345
申请日：2001-07-16
申请人： Shane L. Bell , Matthew C. Mattina
发明人： Shane L. Bell , Matthew C. Mattina
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/3851
摘要： A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.
摘要翻译：多线程处理器被配置为检测来自第一程序的除外指令，并且停止从该同一程序获取较年轻的指令，从而节省可由其他程序使用的系统资源。每个获取的程序指令都有一个关联的状态位，如果指令除外，则该位被置位。每个除了指令都记录在异常记录单元中，这会导致相关的状态位被置位。每个程序都有一个关联的飞行中向量表，跟踪已经为该程序获取的指令。将状态位与飞行中矢量表进行比较，以识别与异常指令相关联的程序。然后该程序被禁用，从而防止进一步获取该程序的指令，直到除外的指令清除为止。

4. 发明授权

US07620954B2 Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors 有权
标题翻译：在基于目录的分布式共享内存多处理器中处理加载锁定/存储条件原语的机制
公开(公告)号：US07620954B2
公开(公告)日：2009-11-17
申请号：US09924934
申请日：2001-08-08
申请人： Matthew C. Mattina , Carl Ramey , Bongjin Jung , Judson Leonard
发明人： Matthew C. Mattina , Carl Ramey , Bongjin Jung , Judson Leonard
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F12/0824 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor. When the Owner processor is ready to resume operation on the data block, the Owner processor again obtains exclusive control of the data block by issuing a Read-with Modify Intent Store Conditional instruction to the Home processor. If the Owner processor is still a sharer, a writeable copy of the data block is sent to the Owner processor, who completes modification of the data block and returns it to the Home processor with a Store Conditional instruction.
摘要翻译：分布式共享存储器系统中的每个处理器具有相关联的存储器和一致性目录。控制内存的处理器是家庭处理器。在某些条件下，另一个处理器可以通过发出一个加载锁定指令，并获得存储在所有者处理器的高速缓存中的数据块的可写拷贝来获得数据块的排他控制。如果所有者处理器在数据块从高速缓存中移位之前未完成数据可写入副本的操作，则它发出受害者共享消息，从而向家庭处理器指示它应该保持为数据块。在另一个处理器寻求对相同数据块的独占权限的情况下，家庭处理器向所有者处理器发出无效消息。当所有者处理器准备好在数据块上恢复操作时，所有者处理器通过向家庭处理器发出读取修改意向存储条件指令，再次获得数据块的排他控制。如果所有者处理器仍然是一个共享者，则可将数据块的可写拷贝发送给所有者处理器，所有者处理器完成对数据块的修改，并使用存储条件指令将其返回到家庭处理器。

5. 发明授权

US07395381B2 Method and an apparatus to reduce network utilization in a multiprocessor system 有权
标题翻译：减少多处理器系统中网络利用率的方法和装置
公开(公告)号：US07395381B2
公开(公告)日：2008-07-01
申请号：US11084423
申请日：2005-03-18
申请人： Matthew C. Mattina
发明人： Matthew C. Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a second processor, checking whether a cache of the first processor stores a copy of data associated with the physical address, and recording an identification (ID) of the second processor if the cache of the first processor stores the copy of data associated with the physical address. Other embodiments have been claimed and described.
摘要翻译：已经公开了一种减少基于源的窥探缓存相干协议的网络利用率的方法和装置。在一个实施例中，该方法包括在第一处理器处接收关于来自第二处理器的多处理器系统中存储器的一部分的物理地址的无效窥探，检查第一处理器的高速缓存是否存储相关联的数据的副本并且如果第一处理器的高速缓存存储与物理地址相关联的数据的副本，则记录第二处理器的标识（ID）。已经要求和描述了其它实施例。

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