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1. 发明申请

US20070186199A1 Heuristic clustering of circuit elements in a circuit design 失效
标题翻译：电路设计中电路元件的启发式聚类
公开(公告)号：US20070186199A1
公开(公告)日：2007-08-09
申请号：US11348970
申请日：2006-02-07
申请人： Mark Fredrickson , Glen Handlogten , Chad McBride
发明人： Mark Fredrickson , Glen Handlogten , Chad McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

2. 发明申请

US20070168797A1 Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree 失效
标题翻译：用于设计用于匹配时钟树门控部分的逻辑扫描链的方法，装置和计算机程序产品
公开(公告)号：US20070168797A1
公开(公告)日：2007-07-19
申请号：US11191417
申请日：2005-07-28
申请人： Mark Fredrickson , Glen Handlogten , Steven Jones , Chad McBride
发明人： Mark Fredrickson , Glen Handlogten , Steven Jones , Chad McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318583
摘要： Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
摘要翻译：提供了用于设计用于匹配时钟树的门控部分的逻辑扫描链的方法，装置和计算机程序产品。时钟树包括多个部分，每个部分包括接收用于特定扫描链的全局时钟和链专用时钟控制信号的输入的门。定义了多个扫描链，每个扫描链包括多个闩锁。每个扫描链锁存器连接到相应的链专用时钟树部分。

3. 发明申请

US20070260949A1 Trading propensity-based clustering of circuit elements in a circuit design 有权
标题翻译：电路设计中电路元件的交易倾向聚类
公开(公告)号：US20070260949A1
公开(公告)日：2007-11-08
申请号：US11348907
申请日：2006-02-07
申请人： Mark Fredrickson , Chad McBride
发明人： Mark Fredrickson , Chad McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318357 , G01R31/318536 , G06F17/5045
摘要： An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
摘要翻译：装置，程序产品和方法利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。

4. 发明申请

US20070186204A1 Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout 失效
标题翻译：基于物理布局的集成电路设计的功能定义的自动背面注释
公开(公告)号：US20070186204A1
公开(公告)日：2007-08-09
申请号：US11348877
申请日：2006-02-07
申请人： Mark Fredrickson , Glen Handlogten , Chad McBride
发明人： Mark Fredrickson , Glen Handlogten , Chad McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译：一种装置，程序产品和方法基于从功能定义生成的物理布局自动地回溯电路设计的功能定义。电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

5. 发明申请

US20070038797A1 Methods and apparatus for invalidating multiple address cache entries 有权
标题翻译：使多个地址缓存条目无效的方法和装置
公开(公告)号：US20070038797A1
公开(公告)日：2007-02-15
申请号：US11201971
申请日：2005-08-11
申请人： Chad McBride , Andrew Wottreng
发明人： Chad McBride , Andrew Wottreng
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0891
摘要： In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种从地址高速缓存中移除条目的第一方法。第一种方法包括以下步骤：（1）将数据写入寄存器; 和（2）基于写入寄存器的数据从地址高速缓存中移除多个地址高速缓存条目。提供了许多其他方面。

6. 发明申请

US20160283415A1 DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING 有权
标题翻译：直接存储器访问描述符处理
公开(公告)号：US20160283415A1
公开(公告)日：2016-09-29
申请号：US14671811
申请日：2015-03-27
申请人： Chad McBride , Jeffrey Bradford , Steven Wheeler , Christopher Johnson , Boris Bobrov , Andras Tantos
发明人： Chad McBride , Jeffrey Bradford , Steven Wheeler , Christopher Johnson , Boris Bobrov , Andras Tantos
IPC分类号： G06F13/16 , G06F13/42 , G06F13/28 , G06F13/40
CPC分类号： G06F13/1642 , G06F13/28 , G06F13/4068 , G06F13/42
摘要： Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.
摘要翻译：使用这样的技术提供硬件加速跨多个直接存储器访问（DMA）引擎的同步，其中描述符处理的顺序对于涉及单个CPU和多个DMA引擎以及涉及多个CPU和多个DMA引擎的情况而言是有保证的。

7. 发明申请

US20070186046A1 Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes 有权
标题翻译：用于虚拟锁定的伪LRU算法在软件和硬件地址转换缓存未命中处理模式下
公开(公告)号：US20070186046A1
公开(公告)日：2007-08-09
申请号：US11348971
申请日：2006-02-07
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/6042
摘要： The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement
摘要翻译：本发明提供了一种用于计算处理器高速缓存中的替换方式的改进方法，该替换方式对于硬件地址转换高速缓存未命中处理，软件地址转换高速缓存未命中处理和提示锁定位的不同组合是有效的。对于一些实施例，仅当禁用软件地址转换高速缓存未命中处理时，才更新用于选择用于替换的条目的LRU位。此外，对于一些实施例，可以修改LRU比特以改变遍历二叉树结构的方式，以避免选择用于替换的提示锁定条目

8. 发明申请

US20070180195A1 Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations 失效
标题翻译：允许不间断地址转换同时执行地址转换高速缓存无效和其它高速缓存操作的方法和装置
公开(公告)号：US20070180195A1
公开(公告)日：2007-08-02
申请号：US11344900
申请日：2006-02-01
申请人： Chad McBride , Andrew Wottreng , John Irish
发明人： Chad McBride , Andrew Wottreng , John Irish
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
摘要翻译：一种用于允许多个设备访问地址转换高速缓存并且同时进行高速缓存维护操作的方法和装置。通过将需要地址转换的命令与可能通常需要许多周期的维护操作交错，与维护操作被允许停止需要地址转换的命令直到维护操作完成之前，地址转换请求可能具有对地址转换缓存的更快访问。

9. 发明申请

US20070180157A1 Method for cache hit under miss collision handling 审中-公开
标题翻译：错误碰撞处理下缓存命中的方法
公开(公告)号：US20070180157A1
公开(公告)日：2007-08-02
申请号：US11344909
申请日：2006-02-01
申请人： John Irish , Chad McBride , Ibrahim Ouda
发明人： John Irish , Chad McBride , Ibrahim Ouda
IPC分类号： G06F3/00
CPC分类号： G06F12/1027 , G06F12/0855 , G06F2212/684
摘要： Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. If address translation entries for a command are not found, the translation entries may be retrieved from memory. Address translations for subsequent commands depending from the command getting the miss may be preserved until the address translation entry is retrieved from memory. Therefore, retranslation of addresses for subsequent commands is avoided.
摘要翻译：本发明的实施例提供了在处理命令队列中的命令时维持命令顺序的方法和系统。命令可能在CPU的输入命令队列中排队。在命令的地址转换期间，可以处理后续命令以提高效率。处理的命令可以放置在输出队列中并按顺序发送到CPU。如果没有找到命令的地址转换条目，则可以从存储器检索翻译条目。从命令获取未命中取得的后续命令的地址转换可以被保留，直到从存储器检索到地址转换条目为止。因此，避免了后续命令的地址重新转发。

10. 发明申请

US20070180156A1 Method for completing IO commands after an IO translation miss 审中-公开
标题翻译：在IO翻译错过后完成IO命令的方法
公开(公告)号：US20070180156A1
公开(公告)日：2007-08-02
申请号：US11344908
申请日：2006-02-01
申请人： John Irish , Chad McBride , Ibrahim Ouda
发明人： John Irish , Chad McBride , Ibrahim Ouda
IPC分类号： G06F3/00
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/684
摘要： Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs the relevant translation cache entries may be retrieved from memory. After the relevant entries are retrieved a notification may be sent requesting reissue of the command getting the translation cache miss.
摘要翻译：本发明的实施例提供了在处理转换高速缓存未命中时在命令队列中处理命令时维持命令顺序的方法和系统。命令可能在CPU的输入命令队列中排队。在命令的地址转换期间，可以处理后续命令以提高效率。处理的命令可以放置在输出队列中并按顺序发送到CPU。在地址转换期间，如果翻译高速缓存未命中，则可以从存储器检索相关的转换高速缓存条目。在检索到相关条目之后，可以发送请求重新发出获得翻译高速缓存未命中的命令的通知。

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