专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06105125A High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information 失效
标题翻译：用于使用分割式微ROM访问的处理器的高速，可扩展的基于微码的指令解码器，动态通用微指令和具有预解码指令信息的微代码
公开(公告)号：US06105125A
公开(公告)日：2000-08-15
申请号：US968976
申请日：1997-11-12
申请人： Mario Nemirovsky , Shailaja Chenumalla
发明人： Mario Nemirovsky , Shailaja Chenumalla
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/223 , G06F9/267 , G06F9/30145
摘要： A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space. The invention also includes the generation of a generic microinstruction dynamically by using the predecoded information selected from the entry microcode table. This makes the generic microinstruction flexible and hence, it can be efficiently be used for many instructions. An entry microcode table, used for the efficient decode of an instruction, contains predecoded information about the instruction apart from the regular microinstruction, which is used directly to generate the decoder outputs and to select the correct microcode entry, and also for the generation of the generic microcode entry. The invention also includes accessing the entry ROM and the .mu.ROM in parallel, using the same address which is generated from the opcode and ModR/M bytes, and selecting one of their outputs. Thus the two ROMs are used efficiently in that the required time and logic are reduced.
摘要翻译：一种用于微处理器的基于微码的解码器电路，其使用快速访问表来解码指令。指向表的指针直接从指令预取缓冲区生成。关于指令的信息位被添加到表中，而不需要额外的成本，并且使得能够更快地解码指令。本发明包括使用入口ROM的指令的解码，其包含关于可以直接用于生成解码器输出的指令的信息。该信息还用于选择正确的ROM条目，从而增强解码器的灵活性，并且动态地生成通用微代码条目。因此，减少了微代码空间的要求。通用的微代码指令用于常用的类似宏指令。这避免了微代码指令的重复，从而减少了所需的微代码空间。本发明还包括通过使用从入口微代码表中选择的预解码信息来动态地生成通用微指令。这使得通用微指令灵活，因此可以有效地用于许多指令。用于指令的有效解码的入口微代码表包含关于除常规微指令之外的指令的预解码信息，其直接用于生成解码器输出并选择正确的微代码条目，并且还用于生成通用微代码条目。本发明还包括使用从操作码和ModR / M字节产生的相同地址并且选择其输出之一并行地访问条目ROM和mu ROM。因此，有效地使用了两个ROM，因为减少了所需的时间和逻辑。

IPRDB

热门服务

关于我们

友情链接

联系方式