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1. 发明申请

US20080228950A1 MEMORY POWER DOWN MODE EXIT METHOD AND SYSTEM 审中-公开
标题翻译：存储器掉电模式退出方法和系统
公开(公告)号：US20080228950A1
公开(公告)日：2008-09-18
申请号：US11686067
申请日：2007-03-14
申请人： Margaret Clark Freebern , Farrukh Aquil , Wolfgang Hokenmaier
发明人： Margaret Clark Freebern , Farrukh Aquil , Wolfgang Hokenmaier
IPC分类号： G06F3/00
CPC分类号： G11C7/1045 , G11C5/143 , G11C11/4074 , G11C2207/2227
摘要： A memory includes a circuit having a set terminal for receiving an input signal indicating a request to exit a power-down mode. The circuit is configured to provide an output signal to enable exiting the power-down mode in response to the input signal before the input signal is latched.
摘要翻译：存储器包括具有用于接收指示退出掉电模式的请求的输入信号的设置终端的电路。电路被配置为提供输出信号，以便在输入信号被锁存之前响应于输入信号而退出掉电模式。

2. 发明授权

US07447107B2 Random access memory including multiple state machines 有权
标题翻译：随机存取存储器包括多个状态机
公开(公告)号：US07447107B2
公开(公告)日：2008-11-04
申请号：US11453946
申请日：2006-06-15
申请人： Margaret Clark Freebern
发明人： Margaret Clark Freebern
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1066 , G11C8/18 , G11C2207/104
摘要： A random access memory including multiple state machines and selection circuitry. The multiple state machines include a first state machine and a second state machine, and possibly more state machines. The first state machine is configured to provide first signals to control the random access memory and provide first command operations and the second state machine is configured to provide second signals to control the random access memory and provide second command operations. The selection circuitry selects one of the multiple state machines. The selection circuitry conducts the first signals to select the first state machine and provide the first command operations and the selection circuitry conducts the second signals to select the second state machine and provide the second command operations.
摘要翻译：包括多个状态机和选择电路的随机存取存储器。多状态机包括第一状态机和第二状态机，以及可能更多的状态机。第一状态机被配置为提供第一信号以控制随机存取存储器并提供第一命令操作，并且第二状态机被配置为提供第二信号以控制随机存取存储器并提供第二命令操作。选择电路选择多个状态机之一。选择电路执行第一信号以选择第一状态机并提供第一命令操作，并且选择电路进行第二信号以选择第二状态机并提供第二命令操作。

3. 发明授权

US07330391B2 Memory having directed auto-refresh 有权
标题翻译：内存指示自动刷新
公开(公告)号：US07330391B2
公开(公告)日：2008-02-12
申请号：US11251678
申请日：2005-10-17
申请人： Margaret Clark Freebern
发明人： Margaret Clark Freebern
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C8/12 , G11C11/40603 , G11C11/40611 , G11C11/40618
摘要： A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh.
摘要翻译：存储器包括至少两个存储器组，每个存储体包括包括行和列的存储单元阵列。存储器包括定向自动刷新存储器组选择电路，其被配置为同时选择用于读取或写入操作的至少两个存储器组中的第一存储器组，以及用于定向自动刷新的至少两个存储器组中的第二存储器组。

4. 发明授权

US07433261B2 Directed auto-refresh for a dynamic random access memory 失效
标题翻译：定向自动刷新动态随机存取存储器
公开(公告)号：US07433261B2
公开(公告)日：2008-10-07
申请号：US11251683
申请日：2005-10-17
申请人： Margaret Clark Freebern , Kazimierz Szczypinski
发明人： Margaret Clark Freebern , Kazimierz Szczypinski
IPC分类号： G11C8/06 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/408
CPC分类号： G11C8/12 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4082
摘要： A memory includes a row address latch. The row address latch includes a first stage configured to latch a row address for a memory read or write operation, and a second stage configured to latch a row address for a memory bank auto-refresh. The row address latch provides the row address from the first stage in response to an activate command and provides the row address from the second stage in response to a directed auto-refresh command.
摘要翻译：存储器包括行地址锁存器。行地址锁存器包括被配置为锁存用于存储器读或写操作的行地址的第一级，以及被配置为锁存用于存储体自动刷新的行地址的第二级。行地址锁存器响应于激活命令从第一级提供行地址，并响应于定向自动刷新命令从第二级提供行地址。

5. 发明申请

US20070297268A1 Random access memory including multiple state machines 有权
标题翻译：随机存取存储器包括多个状态机
公开(公告)号：US20070297268A1
公开(公告)日：2007-12-27
申请号：US11453946
申请日：2006-06-15
申请人： Margaret Clark Freebern
发明人： Margaret Clark Freebern
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1066 , G11C8/18 , G11C2207/104
摘要： A random access memory including multiple state machines and selection circuitry. The multiple state machines include a first state machine and a second state machine, and possibly more state machines. The first state machine is configured to provide first signals to control the random access memory and provide first command operations and the second state machine is configured to provide second signals to control the random access memory and provide second command operations. The selection circuitry selects one of the multiple state machines. The selection circuitry conducts the first signals to select the first state machine and provide the first command operations and the selection circuitry conducts the second signals to select the second state machine and provide the second command operations.
摘要翻译：包括多个状态机和选择电路的随机存取存储器。多状态机包括第一状态机和第二状态机，以及可能更多的状态机。第一状态机被配置为提供第一信号以控制随机存取存储器并提供第一命令操作，并且第二状态机被配置为提供第二信号以控制随机存取存储器并提供第二命令操作。选择电路选择多个状态机之一。选择电路执行第一信号以选择第一状态机并提供第一命令操作，并且选择电路进行第二信号以选择第二状态机并提供第二命令操作。

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