专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5896338A Input/output power supply detection scheme for flash memory 失效
标题翻译：闪存输入/输出电源检测方案
公开(公告)号：US5896338A
公开(公告)日：1999-04-20
申请号：US837001
申请日：1997-04-11
申请人： Marcus E. Landgraf , Robert E. Larsen , Mase J. Taub , Sanjay Talreja , Vishram P. Dalvi , Edward M. Babb , Bharat M. Pathak , Christopher J. Haid
发明人： Marcus E. Landgraf , Robert E. Larsen , Mase J. Taub , Sanjay Talreja , Vishram P. Dalvi , Edward M. Babb , Bharat M. Pathak , Christopher J. Haid
IPC分类号： G11C16/22 , G11C13/00
CPC分类号： G11C16/225
摘要： A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.
摘要翻译：描述防止非易失性可写存储器数据的损坏的电源锁定电路。电源锁定电路监视来自多个电源的电源信号。当耦合到非易失性可写存储器的所监视的电源信号中的任何一个低于指定信号电平时，电源锁定电路锁定写入非易失性可写存储器的命令。电源锁定电路包括当电源信号小于预定电压时向非易失性可写存储器提供锁定信号的检测器。电源锁定电路还包括采样电路，当不同的电源信号小于参考电压时，该采样电路向非易失性可写入存储器提供其它锁定信号。

2. 发明授权

US5933026A Self-configuring interface architecture on flash memories 失效
标题翻译：闪存上的自配置接口架构
公开(公告)号：US5933026A
公开(公告)日：1999-08-03
申请号：US834026
申请日：1997-04-11
申请人： Robert E. Larsen , Harry Q. Pon , Sanjay Talreja , Marcus E. Landgraf , Ranjeet Alexis
发明人： Robert E. Larsen , Harry Q. Pon , Sanjay Talreja , Marcus E. Landgraf , Ranjeet Alexis
IPC分类号： G11C5/14 , G11C7/10 , H03K19/0185
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1051 , G11C7/1078 , H03K19/018585
摘要： A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.
摘要翻译：描述了用于非易失性可写存储器的低功率接口。该接口包括一个输入缓冲区和一个输出缓冲区。输入缓冲器接收具有多对逻辑电平中的一个的输入信号。输入缓冲器耦合到非易失性可写存储器并且耦合到与非易失性可写存储器相同的电源。输入缓冲器将接收到的输入信号转换为由非易失性可写存储器使用的信号电平。输出缓冲器耦合到非易失性可写存储器，并且被耦合到来自输入缓冲器和非易失性可写存储器的不同电源。输出缓冲器将从非易失性可写存储器接收的信号转换为与输入信号相同的信号电平。输入缓冲器和输出缓冲器利用具有与互补金属氧化物半导体（CMOS）技术兼容的逻辑电平的输入/输出信号。

3. 发明授权

US6088264A Flash memory partitioning for read-while-write operation 失效
标题翻译：用于读写操作的闪存分区
公开(公告)号：US6088264A
公开(公告)日：2000-07-11
申请号：US2649
申请日：1998-01-05
申请人： Peter K. Hazen , Ranjeet Alexis , Robert E. Larsen , Charles W. Brown , Sanjay Talreja
发明人： Peter K. Hazen , Ranjeet Alexis , Robert E. Larsen , Charles W. Brown , Sanjay Talreja
IPC分类号： G11C16/02 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/10 , G11C16/26 , G11C2216/22
摘要： A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.
摘要翻译：提供了一种用于分区闪速存储器件的方法和装置。闪存设备包括多个分区，每个分区能够与其他分区同时读取，写入或擦除。

4. 发明授权

US5684741A Auto-verification of programming flash memory cells 失效
标题翻译：编程闪存单元的自动验证
公开(公告)号：US5684741A
公开(公告)日：1997-11-04
申请号：US578505
申请日：1995-12-26
申请人： Sanjay Talreja
发明人： Sanjay Talreja
IPC分类号： G11C16/28 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3486 , G11C16/28 , G11C16/3468 , G11C16/3481
摘要： A method for verifying that a flash EEPROM memory device has reached a programmed state including the steps of providing a programming pulse of a preselected level and unspecified duration to the device, monitoring the current through the device as the programming pulse is applied, and providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a programmed device.
摘要翻译：一种用于验证闪存EEPROM存储器件已经达到编程状态的方法，包括以下步骤：向所述器件提供预选电平和未指定持续时间的编程脉冲，当应用编程脉冲时监视通过器件的电流，并提供一个当通过器件的电流达到等于通过编程器件的电流时，终止编程脉冲的信号。

5. 发明授权

US5828616A Sensing scheme for flash memory with multilevel cells 失效
公开(公告)号：US5828616A
公开(公告)日：1998-10-27
申请号：US801004
申请日：1997-02-19
申请人： Mark E. Bauer , Sanjay Talreja , Albert Fazio , Gregory Atwood , Johnny Javanifard , Kevin W. Frary
发明人： Mark E. Bauer , Sanjay Talreja , Albert Fazio , Gregory Atwood , Johnny Javanifard , Kevin W. Frary
IPC分类号： G11C13/00 , G11C11/56 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

6. 发明申请

US20060143371A1 Integrated memory management apparatus, systems, and methods 审中-公开
标题翻译：集成内存管理设备，系统和方法
公开(公告)号：US20060143371A1
公开(公告)日：2006-06-29
申请号：US11023777
申请日：2004-12-28
申请人： John Rudelic , Sanjay Talreja , Mickey Fandrich
发明人： John Rudelic , Sanjay Talreja , Mickey Fandrich
IPC分类号： G06F13/00
CPC分类号： G06F13/1668
摘要： Apparatus and systems, as well as methods and articles, may perform operations including memory bank management and memory bus arbitration associated with a first memory module comprising non-refreshable memory cells and a controller, a second memory module coupled to the first memory module by a memory management control bus, or both. Some embodiments may also perform precharge and refresh operations associated with the second memory module.
摘要翻译：设备和系统以及方法和物品可以执行包括与包括不可刷新存储器单元和控制器的第一存储器模块相关联的存储体管理和存储器总线仲裁的操作，第二存储器模块，其通过内存管理控制总线，或两者兼容。一些实施例还可以执行与第二存储器模块相关联的预充电和刷新操作。

7. 发明授权

US5748546A Sensing scheme for flash memory with multilevel cells 失效
标题翻译：具有多电平单元的闪存感测方案
公开(公告)号：US5748546A
公开(公告)日：1998-05-05
申请号：US827670
申请日：1997-04-10
申请人： Mark E. Bauer , Sanjay Talreja , Kevin W. Frary , Gregory Atwood , Albert Fazio , Johnny Javanifard
发明人： Mark E. Bauer , Sanjay Talreja , Kevin W. Frary , Gregory Atwood , Albert Fazio , Johnny Javanifard
IPC分类号： G11C13/00 , G11C11/56 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.
摘要翻译：公开了用于确定具有多于两种可能状态的存储单元的状态的方法和装置。对于第一实施例，通过选择性地将所选择的存储器单元的阈值电压Vt与（n-1）个参考电压进行比较来确定具有n个状态的闪存单元的状态，其中n是2的幂。对于每两个状态，提供单个比较器，使得比较器的总数等于存储在存储单元中的位数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式