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1. 发明授权

US08598633B2 Semiconductor device having contact layer providing electrical connections 有权
标题翻译：具有提供电连接的接触层的半导体器件
公开(公告)号：US08598633B2
公开(公告)日：2013-12-03
申请号：US13351101
申请日：2012-01-16
申请人： Marc Tarabbia , James B. Gullette , Mahbub Rashed , David S. Doman , Irene Y. Lin , Ingolf Lorenz , Larry Ho , Chinh Nguyen , Jeff Kim , Jongwook Kye , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Jason E. Stephens , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
发明人： Marc Tarabbia , James B. Gullette , Mahbub Rashed , David S. Doman , Irene Y. Lin , Ingolf Lorenz , Larry Ho , Chinh Nguyen , Jeff Kim , Jongwook Kye , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Jason E. Stephens , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L21/76895 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
摘要翻译：半导体器件包括具有扩散区域的半导体衬底。晶体管形成在扩散区内。电力轨设置在扩散区域的外侧。接触层设置在基板上方和电源轨下方。通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

2. 发明申请

US20130181289A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130181289A1
公开(公告)日：2013-07-18
申请号：US13351101
申请日：2012-01-16
申请人： Marc Tarabbia , James B. Gullette , Mahbub Rashed , David S. Doman , Irene Y. Lin , Ingolf Lorenz , Larry Ho , Chinh Nguyen , Jeff Kim , Jongwook Kye , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Jason E. Stephens , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
发明人： Marc Tarabbia , James B. Gullette , Mahbub Rashed , David S. Doman , Irene Y. Lin , Ingolf Lorenz , Larry Ho , Chinh Nguyen , Jeff Kim , Jongwook Kye , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Jason E. Stephens , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L23/5286 , H01L21/76895 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
摘要翻译：半导体器件包括具有扩散区域的半导体衬底。晶体管形成在扩散区内。电力轨设置在扩散区域的外侧。接触层设置在基板上方和电源轨下方。通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

3. 发明申请

US20130146982A1 SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS 有权
标题翻译：具有晶体管局部互连的半导体器件
公开(公告)号：US20130146982A1
公开(公告)日：2013-06-13
申请号：US13324699
申请日：2011-12-13
申请人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L27/088
CPC分类号： H01L21/76895 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
摘要翻译：提供半导体器件用于实现至少一个逻辑元件。半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。

4. 发明授权

US08581348B2 Semiconductor device with transistor local interconnects 有权
标题翻译：具有晶体管局部互连的半导体器件
公开(公告)号：US08581348B2
公开(公告)日：2013-11-12
申请号：US13324699
申请日：2011-12-13
申请人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L27/088 , H01L21/70 , H01L21/02
CPC分类号： H01L21/76895 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
摘要翻译：提供半导体器件用于实现至少一个逻辑元件。半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。

5. 发明申请

US20140042641A1 MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES 有权
标题翻译：使用扩散接触结构的中间线结构
公开(公告)号：US20140042641A1
公开(公告)日：2014-02-13
申请号：US13568737
申请日：2012-08-07
申请人： Mahbub Rashed , Yuansheng Ma , Irene Lin , Jason Stephens , Yunfei Deng , Yuan Lei , Jongwook Kye , Rod Augur , Shibly Ahmed , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , Yuansheng Ma , Irene Lin , Jason Stephens , Yunfei Deng , Yuan Lei , Jongwook Kye , Rod Augur , Shibly Ahmed , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5386 , H01L21/76895 , H01L21/823871 , H01L23/5384 , H01L27/0207 , H01L27/0924 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
摘要翻译：公开了一种使用扩散接触结构提供MOL构造的方法。实施例包括：在衬底中提供第一扩散区域; 通过第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在扩散间隙区域上提供扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

6. 发明授权

US09006100B2 Middle-of-the-line constructs using diffusion contact structures 有权
标题翻译：使用扩散接触结构的中间线构造
公开(公告)号：US09006100B2
公开(公告)日：2015-04-14
申请号：US13568737
申请日：2012-08-07
申请人： Mahbub Rashed , Yuansheng Ma , Irene Lin , Jason Stephens , Yunfei Deng , Yuan Lei , Jongwook Kye , Rod Augur , Shibly Ahmed , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , Yuansheng Ma , Irene Lin , Jason Stephens , Yunfei Deng , Yuan Lei , Jongwook Kye , Rod Augur , Shibly Ahmed , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L21/4763 , H01L27/02 , H01L21/8238 , H01L21/768
CPC分类号： H01L23/5386 , H01L21/76895 , H01L21/823871 , H01L23/5384 , H01L27/0207 , H01L27/0924 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
摘要翻译：公开了一种使用扩散接触结构提供MOL构造的方法。实施例包括：在衬底中提供第一扩散区域; 经由第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在扩散间隙区域上提供扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

7. 发明授权

US08689154B2 Providing timing-closed FinFET designs from planar designs 有权
标题翻译：从平面设计提供定时关闭的FinFET设计
公开(公告)号：US08689154B2
公开(公告)日：2014-04-01
申请号：US13446418
申请日：2012-04-13
申请人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
摘要翻译：公开了一种从平面设计提供定时关闭的FinFET设计的方法。实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

8. 发明申请

US20130275935A1 PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS 有权
标题翻译：从平面设计提供定时关闭FINFET设计
公开(公告)号：US20130275935A1
公开(公告)日：2013-10-17
申请号：US13446418
申请日：2012-04-13
申请人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
摘要翻译：公开了一种从平面设计提供定时关闭的FinFET设计的方法。实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

9. 发明申请

US20100311242A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100311242A1
公开(公告)日：2010-12-09
申请号：US12480232
申请日：2009-06-08
申请人： Yunfei Deng , Jongwook Kye
发明人： Yunfei Deng , Jongwook Kye
IPC分类号： H01L21/308 , G03B27/42 , G03F7/20 , G03F1/00
CPC分类号： G03F1/00 , G03B27/42 , G03F7/2024 , H01L21/0273
摘要： Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
摘要翻译：提供了制造半导体器件的方法。一种方法包括提供具有第一多边形的第一图案，所述第一多边形具有第一音调并且具有第一侧和第二侧，所述第一侧邻近于具有第二音调的第二多边形，并且所述第二侧相邻于第三多边形具有第二色调的多边形，并且通过反转第一图案的色调来形成第二图案。该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调，从第二图案形成第三图案，通过颠倒第三图案的音调，并通过反转第四图案的音调形成第六图案。

10. 发明授权

US08361335B2 Methods for fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08361335B2
公开(公告)日：2013-01-29
申请号：US12480232
申请日：2009-06-08
申请人： Yunfei Deng , Jongwook Kye
发明人： Yunfei Deng , Jongwook Kye
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： G03F1/00 , G03B27/42 , G03F7/2024 , H01L21/0273
摘要： Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
摘要翻译：提供了制造半导体器件的方法。一种方法包括提供具有第一多边形的第一图案，所述第一多边形具有第一音调并且具有第一侧和第二侧，所述第一侧邻近于具有第二音调的第二多边形，并且所述第二侧相邻于第三多边形具有第二色调的多边形，并且通过反转第一图案的色调来形成第二图案。该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调，从第二图案形成第三图案，通过颠倒第三图案的音调，并通过反转第四图案的音调形成第六图案。

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