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    • 5. 发明授权
    • Timing skew error correction apparatus and methods
    • 定时偏差纠错装置及方法
    • US08269528B2
    • 2012-09-18
    • US12948757
    • 2010-11-18
    • Robert Floyd PaynePhilip M. PrattWilliam David Smith
    • Robert Floyd PaynePhilip M. PrattWilliam David Smith
    • G11C27/02
    • H03M1/0624G11C27/02H03L7/0812H03M1/0836H03M1/1245
    • Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.
    • 本文公开的装置和方法用于补偿出现在模拟信号捕获电路的输入处的模拟信号的反相(例如,差分相位)之间的偏斜,所述模拟信号在诸如跟踪保持或采样保持电路 ADC或类似设备。 两个捕获时钟中的每一个用于捕获一个反相。 一个或多个延迟电路被配置为在与两个捕获时钟相关联的时钟转换之间产生差分延迟。 差分延迟与反相之间的输入偏差成比例。 因此相位在相域轴上的基本相同的点被采样。 实施例操作以产生相位采样同步性,从而降低由偏斜引起的共模信号分量的振幅。 可能导致线性增加和失真减少。
    • 6. 发明申请
    • TIMING SKEW ERROR CORRECTION APPARATUS AND METHODS
    • 时间轴误差校正装置及方法
    • US20120126869A1
    • 2012-05-24
    • US12948757
    • 2010-11-18
    • ROBERT FLOYD PAYNEPhilip M. PrattWilliam David Smith
    • ROBERT FLOYD PAYNEPhilip M. PrattWilliam David Smith
    • H03L7/00
    • H03M1/0624G11C27/02H03L7/0812H03M1/0836H03M1/1245
    • Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.
    • 本文公开的装置和方法用于补偿出现在模拟信号捕获电路的输入处的模拟信号的反相(例如,差分相位)之间的偏斜,所述模拟信号在诸如跟踪保持或采样保持电路 ADC或类似设备。 两个捕获时钟中的每一个用于捕获一个反相。 一个或多个延迟电路被配置为在与两个捕获时钟相关联的时钟转换之间产生差分延迟。 差分延迟与反相之间的输入偏差成比例。 因此相位在相域轴上的基本相同的点被采样。 实施例操作以产生相位采样同步性,从而降低由偏斜引起的共模信号分量的振幅。 可能导致线性增加和失真减少。
    • 10. 发明授权
    • Method and apparatus for reducing noise in analog-to-digital converter devices
    • 降低模数转换器装置噪声的方法和装置
    • US06958723B1
    • 2005-10-25
    • US10803128
    • 2004-03-17
    • Marco CorsiWilliam J. BrightMartin Kithinji KinyuaWilliam David Smith
    • Marco CorsiWilliam J. BrightMartin Kithinji KinyuaWilliam David Smith
    • H03M1/08H03M1/38H03M1/44
    • H03M1/08H03M1/447
    • An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.
    • 模数转换器装置具有多个级。 每个级包括具有第一和第二放大器单元的残余放大器。 每个放大器单元具有第一输入轨迹,第二输入轨迹和输出轨迹。 放大器单元合作在第一输入轨迹处接收差分输入数据信号。 DC电平设定信号单元与第二输入轨迹耦合,并且在第一电流方向上提供直流电平设定电流。 逆流信号产生单元经由与第二输入轨迹共同的单个耦合轨迹与第二输入轨迹耦合,并且在与第一电流方向相反的第二电流方向上向第二输入轨迹提供控制电流信号。 控制电流信号为每个放大器单元提供直流电平控制。