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1. 发明授权

US4794523A Cache memory architecture for microcomputer speed-up board 失效
标题翻译：微机加速板高速缓存存储架构
公开(公告)号：US4794523A
公开(公告)日：1988-12-27
申请号：US782664
申请日：1985-09-30
申请人： Manolito Adan , Steven Meadows , Robert McCaslin
发明人： Manolito Adan , Steven Meadows , Robert McCaslin
IPC分类号： G06F12/08 , G06F9/28
CPC分类号： G06F12/0802
摘要： A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer's main memory, disabling the computer's main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.
摘要翻译：一种用于提高计算机的操作速度的方法和装置包括提供比计算机的主存储器更快的高速缓冲存储器，禁用计算机的主微处理器，并用更快的时钟周期时间的微处理器来代替它。存储在主存储器中的程序的一部分被存储在高速缓冲存储器中。存储在高速缓冲存储器中的主存储器的部分的地址在标签RAM中记录。在执行程序期间的每个寻址序列时，检查标签RAM以确定寻址位置是否存储在高速缓冲存储器中。如果在标签RAM中识别存储的位置，则从高速缓冲存储器中高速检索。否则，以较慢的速度从主存储器中检索地址位置中的数据，并写入高速缓冲存储器，以便可以高速进行后续访问。

2. 发明申请

US20100117850A1 PRECISELY SYNCHRONIZED NOTIFICATION SYSTEM 审中-公开
标题翻译：精密同步通报系统
公开(公告)号：US20100117850A1
公开(公告)日：2010-05-13
申请号：US12613024
申请日：2009-11-05
申请人： Robert McCaslin , Steven F. Meadows
发明人： Robert McCaslin , Steven F. Meadows
IPC分类号： G08B5/00
CPC分类号： G08B5/36 , G08G1/095 , H05B33/0854 , H05B37/0281 , H05B37/029 , Y02B20/42
摘要： A system for producing a notification. The system includes a control device that includes a processor, a master clock operably connected to the processor and configured to produce a master clock signal, a user interface operably connected to the processor and configured to generate an operational sequence based upon a user input, and a transmitter operably connected to the processor and configured to transmit the master clock signal and the operational sequence. The system further includes a plurality of output devices configured to establish a connection with the control device, to receive the master clock signal and the operational sequence via the established connection, and to produce a synchronized notification based upon the master clock signal and the operational sequence. The synchronized notification may include flashing lights, audible sounds, or other similar displays.
摘要翻译：用于生成通知的系统。该系统包括控制设备，其包括处理器，主时钟，其可操作地连接到处理器并且被配置为产生主时钟信号，用户界面可操作地连接到处理器并被配置为基于用户输入生成操作序列，以及发射机，其可操作地连接到所述处理器并且被配置为传送所述主时钟信号和所述操作序列。该系统还包括多个输出装置，其被配置为建立与控制装置的连接，以经由建立的连接来接收主时钟信号和操作序列，并且基于主时钟信号和操作顺序产生同步通知。同步的通知可以包括闪光灯，可听见的声音或其他类似的显示器。

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