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1. 发明申请

US20090265472A1 Method, System, and Apparatus for System Level Initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20090265472A1
公开(公告)日：2009-10-22
申请号：US12348723
申请日：2009-01-05
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

2. 发明授权

US08606934B2 Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components 有权
标题翻译：通过传送组件的功能和标识符来进行系统级初始化的方法，系统和装置
公开(公告)号：US08606934B2
公开(公告)日：2013-12-10
申请号：US12348723
申请日：2009-01-05
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
IPC分类号： G06F3/00 , G06F13/00 , G06F15/16 , G06F15/177 , H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

3. 发明授权

US07738484B2 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US07738484B2
公开(公告)日：2010-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

4. 发明申请

US20060126656A1 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20060126656A1
公开(公告)日：2006-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

5. 发明申请

US20150006871A1 CONTROLLING ACCESS TO STORAGE IN A COMPUTING DEVICE 有权
标题翻译：控制访问计算机设备中的存储
公开(公告)号：US20150006871A1
公开(公告)日：2015-01-01
申请号：US13930643
申请日：2013-06-28
申请人： Murugasamy Nachimuthu , Mohan Kumar , Dimitrios Ziakas
发明人： Murugasamy Nachimuthu , Mohan Kumar , Dimitrios Ziakas
IPC分类号： G06F12/14 , G06F21/57
CPC分类号： G06F12/1408 , G06F21/575 , G06F21/78
摘要： In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.
摘要翻译：在一个实施例中，计算设备可以包括控制单元。控制单元可以从包含在计算设备中的中央处理单元（CPU）获取可能正在执行与计算设备相关联的基本输入/输出系统（BIOS）的请求。请求可以包括对可能表示包含在计算设备中的存储的最大授权存储大小的值的请求。控制单元可以生成值并将值发送到CPU。 CPU可以基于该值生成系统地址映射。 CPU可以将系统地址映射发送到控制单元，控制单元可以基于所获取的系统地址映射来获取系统地址映射并且配置包含在计算设备中的地址解码器。

6. 发明申请

US20200320033A1 [RSA OR HARVESTING] UNIFIED FPGA VIEW TO A COMPOSED HOST 审中-公开
公开(公告)号：US20200320033A1
公开(公告)日：2020-10-08
申请号：US16905395
申请日：2020-06-18
申请人： Mohan Kumar , Murugasamy Nachimuthu
发明人： Mohan Kumar , Murugasamy Nachimuthu
IPC分类号： G06F13/40 , G06F9/455 , G06F15/78 , G06F9/50
摘要： Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

7. 发明授权

US07640453B2 Methods and apparatus to change a configuration of a processor system 失效
标题翻译：改变处理器系统配置的方法和装置
公开(公告)号：US07640453B2
公开(公告)日：2009-12-29
申请号：US11618422
申请日：2006-12-29
申请人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
发明人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
IPC分类号： G06F11/00
CPC分类号： G06F9/4812 , G06F9/5061
摘要： Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.
摘要翻译：公开了改变处理器系统的配置的方法和装置。一个示例公开的方法在处理系统的非静默状态期间计算系统配置数据，在处理系统的非静止状态期间将基于所计算的系统配置数据的信息存储在数据缓冲器中，并且从数据缓冲器中提取信息在处理系统处于静止状态时更新处理系统的配置。

8. 发明授权

US09342394B2 Secure error handling 有权
标题翻译：安全错误处理
公开(公告)号：US09342394B2
公开(公告)日：2016-05-17
申请号：US13997301
申请日：2011-12-29
申请人： Murugasamy Nachimuthu , Mohan J. Kumar , Theodros Yigzaw , Jose A. Vargas , Rajender Kuramkote
发明人： Murugasamy Nachimuthu , Mohan J. Kumar , Theodros Yigzaw , Jose A. Vargas , Rajender Kuramkote
IPC分类号： G06F11/00 , G06F11/07 , G06F11/36 , G06F21/57
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
摘要： Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
摘要翻译：本文描述了各种实施例。一些实施例包括操作系统和平台。该平台包括具有错误寄存器的处理器。操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。描述和要求保护其他实施例。

9. 发明申请

US20080307082A1 Dynamically discovering a system topology 有权
标题翻译：动态发现系统拓扑
公开(公告)号：US20080307082A1
公开(公告)日：2008-12-11
申请号：US11810434
申请日：2007-06-05
申请人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
发明人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
IPC分类号： G06F15/173
CPC分类号： G06F15/17337 , G06F15/177
摘要： In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于动态发现具有多个点对点（PTP）链路的系统的拓扑的方法，所述系统经由将链路交换的参数与耦合到系统引导的至少一个组件进行通信的例程处理器（SBSP）基于通信设置最小的路由基础设施信息集合，并且基于使用最小路由基础设施信息集从SBSP到目标组件的通信来确定邻近组件到目标组件的存在。描述和要求保护其他实施例。

10. 发明申请

US20070157011A1 Fault resilient boot in multi-processor systems 有权
标题翻译：多处理器系统中的故障恢复启动
公开(公告)号：US20070157011A1
公开(公告)日：2007-07-05
申请号：US11322997
申请日：2005-12-30
申请人： Mohan Kumar , Murugasamy Nachimuthu
发明人： Mohan Kumar , Murugasamy Nachimuthu
IPC分类号： G06F15/177
CPC分类号： G06F11/1417 , G06F11/0724 , G06F11/0757
摘要： In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.
摘要翻译：在一些实施例中，监视多处理器系统中的系统引导带处理器的引导进程，并且使用应用处理器检测引导处理器故障。如果检测到引导处理器故障，系统的至少一部分将被重新初始化（和/或系统重新启动）。描述和要求保护其他实施例。

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