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1. 发明授权

US09519013B2 Mode-controlled voltage excursion detector apparatus and a method of operating thereof 有权
标题翻译：模式控制电压偏移检测装置及其操作方法
公开(公告)号：US09519013B2
公开(公告)日：2016-12-13
申请号：US14445679
申请日：2014-07-29
申请人： Manfred Thanner , Carl Culshaw , Sunny Gupta
发明人： Manfred Thanner , Carl Culshaw , Sunny Gupta
IPC分类号： G01R31/40 , G01R19/165
CPC分类号： G01R19/16552
摘要： A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.
摘要翻译：描述了用于监视施加到负载的电源的电源电压的模式控制的电压偏移检测器装置及其操作方法。电压监视器被配置为如果电源电压超过或低于至少一个定义的阈值，则检测偏移事件，以便在检测到偏移事件时产生偏移事件信号，并将生成的偏移事件信号提供给偏移事件输出通过偏移事件输出输出。灵敏度控制模块被配置为接收指示潜在电压偏移的信号。灵敏度控制模块进一步可操作地耦合到灵敏度控制输入，并且被配置为响应于触发禁止输出的信号的接收而禁止在限定的时间段内产生的偏移事件信号的输出。

2. 发明授权

US09841795B2 Method for resetting an electronic device having independent device domains 有权
公开(公告)号：US09841795B2
公开(公告)日：2017-12-12
申请号：US14492711
申请日：2014-09-22
申请人： Carl Culshaw , Sunny Gupta , Thomas Henry Luedeke , Deboleena Sakalley
发明人： Carl Culshaw , Sunny Gupta , Thomas Henry Luedeke , Deboleena Sakalley
IPC分类号： H03L7/00 , G06F1/24 , G06F11/07
CPC分类号： G06F1/24 , G06F11/0724 , G06F11/14
摘要： A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

3. 发明授权

US09476937B2 Debug circuit for an integrated circuit 有权
标题翻译：集成电路调试电路
公开(公告)号：US09476937B2
公开(公告)日：2016-10-25
申请号：US14514403
申请日：2014-10-15
申请人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
发明人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
IPC分类号： G01R31/317
CPC分类号： G01R31/31705
摘要： An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.
摘要翻译：在功能和调试模式下可操作的集成电路（IC）包括调试使能电路，焊盘控制寄存器，调试电路，焊盘配置寄存器和输入/输出（IO）焊盘。调试电路接收来自电路监视电路的功能信号，参考信号，来自调试使能电路的调试控制信号，以及来自焊盘控制寄存器的上拉使能控制和拉取型选择控制信号，并产生上拉使能和拉式选择信号。焊盘配置寄存器接收拉电阻和上拉选择信号，并将IO焊盘配置为逻辑低电平，逻辑高电阻和高阻抗状态之一。当IO垫处于比预定时间段长的逻辑高和低状态中的任何一个时，则IO垫指示IC保持在复位序列的复位阶段。

4. 发明申请

US20130093505A1 ON-CHIP VOLTAGE REGULATOR 有权
标题翻译：片内电压调节器
公开(公告)号：US20130093505A1
公开(公告)日：2013-04-18
申请号：US13275310
申请日：2011-10-17
申请人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
摘要翻译：用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端表示SoC的运行状况的属性。第二个属性可能在SoC的一系列操作条件下变化。比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

5. 发明申请

US20160098047A1 VOLTAGE MONITORING SYSTEM 有权
标题翻译：电压监测系统
公开(公告)号：US20160098047A1
公开(公告)日：2016-04-07
申请号：US14509039
申请日：2014-10-07
申请人： Kumar Abhishek , Aniruddha Gupta , Sunny Gupta , Nitin Pant
发明人： Kumar Abhishek , Aniruddha Gupta , Sunny Gupta , Nitin Pant
IPC分类号： G05F1/46 , H03M1/66
CPC分类号： G05F1/462
摘要： An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.
摘要翻译：集成电路（IC）包括数模转换器（DAC），电压监视电路和控制器。电压监控电路包括产生LVD和LVW参考电压信号的低电压检测（LVD）和低电压警告（LVW）电路。控制器产生并存储电压裕度字（分别对应于LVD和LVW参考电压信号的第一和第二DAC字之间的差异）。控制器将电压裕度字与预定的最大和最小电压裕度字进行比较。如果电压裕度字不在预定的最大和最小电压裕度字之间，则控制器产生缩放LVW参考电压信号的电压调整信号。在缩放之后，如果电压裕度字位于预定的最大和最小电压裕度字之间，则控制器产生校准通过信号，否则控制器产生校准失败信号。

6. 发明申请

US20150194886A1 VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT 有权
标题翻译：集成电路电压调节系统
公开(公告)号：US20150194886A1
公开(公告)日：2015-07-09
申请号：US14150725
申请日：2014-01-08
申请人： Pedro Barbosa Zanetta , Kumar Abhishek , Sunny Gupta , Nitin Pant
发明人： Pedro Barbosa Zanetta , Kumar Abhishek , Sunny Gupta , Nitin Pant
IPC分类号： H02M3/158 , H03K3/012
CPC分类号： H02M3/158 , G05F1/565 , G05F1/569 , G05F1/571 , G05F1/573 , G06F1/26 , H02M2001/0032 , H03K19/0013
摘要： An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.
摘要翻译：具有电压调节的集成电路（IC）包括大功率和低功率域，低压和高压调节器以及低功率调节器。当IC处于高功率模式时，低压稳压器为高电源和低电源供电。当IC处于低功耗模式时，低功率稳压器从高电压调节器接收电压并为低功率域供电。该IC包括一个切换模块，当高电压调节器的输出电压低于上电期间的阈值电压时，将低压调节器与低功率域断开连接，并将低电压调节器连接到低功率域，当电压由高压调节器调节器超过阈值电压。

7. 发明授权

US09000968B1 Analog-to-digital converter with clock halting circuit 有权
标题翻译：具有时钟停止电路的模数转换器
公开(公告)号：US09000968B1
公开(公告)日：2015-04-07
申请号：US14108294
申请日：2013-12-16
申请人： Sunny Gupta , Kumar Abhishek , Nitin Pant
发明人： Sunny Gupta , Kumar Abhishek , Nitin Pant
IPC分类号： H03M1/12 , H03M1/08 , H03M1/00
CPC分类号： H03M1/0624 , H03M1/12
摘要： An analog to digital converter (ADC) includes a clock-halting circuit that is enabled by an externally generated trigger signal. The clock-halting circuit halts an input clock signal to the ADC for a predetermined time period and resumes the input clock signal to the ADC when the predetermined time period ends.
摘要翻译：模数转换器（ADC）包括由外部产生的触发信号使能的时钟停止电路。时钟停止电路将输入时钟信号暂停到ADC预定时间段，并在预定时间段结束时将输入时钟信号恢复到ADC。

8. 发明授权

US08923958B2 System and method for evaluating an electrophysiological signal 有权
标题翻译：用于评估电生理信号的系统和方法
公开(公告)号：US08923958B2
公开(公告)日：2014-12-30
申请号：US13605364
申请日：2012-09-06
申请人： Sunny Gupta , Mohsen Najafi Yazdi
发明人： Sunny Gupta , Mohsen Najafi Yazdi
IPC分类号： A61B5/0402 , A61B5/0476 , A61B5/04 , A61B5/044 , A61B5/0452 , A61B5/0245 , A61B5/00 , A61B5/046 , A61B5/0464 , A61B5/02 , A61B5/055 , A61B6/03 , G06K9/00
CPC分类号： A61B5/04012 , A61B5/02028 , A61B5/0245 , A61B5/04011 , A61B5/044 , A61B5/0452 , A61B5/04525 , A61B5/046 , A61B5/0464 , A61B5/055 , A61B5/4848 , A61B5/4884 , A61B5/7203 , A61B5/7232 , A61B5/7239 , A61B5/7253 , A61B6/032 , G06K9/0051 , G06K9/00536 , G16H50/50
摘要： A method of evaluating an electrophysiological signal is disclosed. A mathematical reconstruction over at least one cycle of the electrophysiological signal is used to identify an abnormal substrate. A non-transitory computer readable medium is also disclosed. The nontransitory computer readable medium has stored thereon instructions for identifying a pathological substrate from a mathematical reconstruction of an electrophysiological signal, which, when executed by a processor, causes the processor to perform steps comprising using a mathematical reconstruction over many cycles of the electrophysiological signal to identify a pathological state. A system for evaluating an electrophysiological signal includes a processor configured to identify a pathological condition from a mathematical reconstruction of the electrophysiological signal. The system also includes a data input coupled to the processor and configured to provide the processor with the electrophysiological signal. The system further includes a user interface coupled to either the processor or the data input.
摘要翻译：公开了评估电生理信号的方法。使用电生理信号的至少一个循环的数学重建来识别异常底物。还公开了一种非暂时的计算机可读介质。非转移性计算机可读介质已经存储有用于从电生理信号的数学重建中识别病理底物的指令，当电子生理信号被数字重建时，其由处理器执行时，使得处理器执行包括在电生理信号的许多周期上进行数学重建的步骤确定病理状态。用于评估电生理信号的系统包括被配置为从电生理信号的数学重建中识别病理状况的处理器。该系统还包括耦合到处理器并被配置为向处理器提供电生理信号的数据输入。系统还包括耦合到处理器或数据输入的用户界面。

9. 发明申请

US20130275936A1 INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD 有权
标题翻译：集成电路电源管理验证方法
公开(公告)号：US20130275936A1
公开(公告)日：2013-10-17
申请号：US13447305
申请日：2012-04-16
申请人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
发明人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.
摘要翻译：用于验证集成电路设计的电源管理的方法包括基于时钟频率和预定义的当前负载模型来估计电路设计中时钟模块的当前负载要求。监测供应给电路设计的电压。当所提供的电压低于电路设计的全油门运行模式的阈值时，第一电压调节器为电路设计提供额外的电流驱动。当电压下降到阈值以下时，第二电压调节器能够升高第一电压调节器的响应时间。

10. 发明授权

US08525597B2 Clock frequency overshoot detection circuit 有权
标题翻译：时钟频率过冲检测电路
公开(公告)号：US08525597B2
公开(公告)日：2013-09-03
申请号：US13288036
申请日：2011-11-03
申请人： Garima Sharda , Sunny Gupta
发明人： Garima Sharda , Sunny Gupta
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , G06F1/04 , H03K5/135 , H03L7/07
摘要： An electronic circuit operating on a first clock signal includes a clock frequency overshoot detection circuit for detecting frequency overshoots in the first clock signal. The clock frequency overshoot detection circuit includes a shift register having an even number plurality of flip-flops. The flip-flops toggle to generate output bit patterns indicative of a frequency overshoot condition. A comparator connected to the shift register generates a comparison signal on detecting the frequency overshoot condition. A latch circuit connected to the comparator generates a frequency overshoot indication signal and the electronic circuit is shifted to a second (or safe) clock signal until the frequency of the first clock signal is rectified.
摘要翻译：在第一时钟信号上工作的电子电路包括用于检测第一时钟信号中的频率过冲的时钟频率过冲检测电路。时钟频率过冲检测电路包括具有偶数个多个触发器的移位寄存器。触发器切换以产生指示频率过冲条件的输出位模式。连接到移位寄存器的比较器在检测频率过冲条件时产生比较信号。连接到比较器的锁存电路产生频率过冲指示信号，电子电路转移到第二（或安全）时钟信号，直到第一时钟信号的频率被纠正为止。

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