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1. 发明授权

US07572683B2 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US07572683B2
公开(公告)日：2009-08-11
申请号：US11558065
申请日：2006-11-09
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L21/331
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了半导体器件的制造方法。反向阻断IGBT通过将p型基极区域和发射极之间延伸的n型漂移区域1的部分引入肖特基接触来形成肖特基结，从而减小反向漏电流和导通电压。

2. 发明授权

US07307330B2 Reverse blocking semiconductor device and a method for manufacturing the same 有权
标题翻译：反向阻挡半导体器件及其制造方法
公开(公告)号：US07307330B2
公开(公告)日：2007-12-11
申请号：US11397478
申请日：2006-04-04
申请人： Michio Nemoto , Manabu Takei , Tatsuya Naito
发明人： Michio Nemoto , Manabu Takei , Tatsuya Naito
IPC分类号： H01L23/58
CPC分类号： H01L29/0646 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/404 , H01L29/7395
摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.
摘要翻译：没有显示隔离区域对反向恢复峰值电流的不利影响的反向阻挡半导体器件，其具有显示令人满意的软恢复的击穿耐受结构，其抑制基本上伴随常规反向阻断IGBT的反向漏电流的恶化，并且公开了令人满意的低导通电压。该器件包括形成在n漂移层上的MOS栅极结构，该MOS栅极结构包括形成在该漂移层的前表面区域中的p +基极层，形成在该基极层的表面区域中的n +发射极区域，覆盖发射极区域和漂移层之间的基底层的表面区域的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。发射极电极与MOS栅极结构的发射极区域和基极层接触。 p +隔离区域通过漂移层包围MOS栅极结构，并延伸穿过漂移层的整个厚度。 p +集电极层形成在漂移层的后表面上并连接到隔离区的后侧。距离W大于厚度d，其中距离W是距离发射电极的一部分的最外侧位置（与基层接触的部分）到隔离区域的最内位置的距离，以及厚度d是漂移层的深度方向的尺寸。

3. 发明申请

US20050082640A1 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US20050082640A1
公开(公告)日：2005-04-21
申请号：US10928927
申请日：2004-08-27
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L29/06 , H01L29/739 , H01L29/872 , H02M7/00 , H01L29/417
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了制造半导体器件的方法。反向阻断IGBT通过将p型基极区域和发射极电极之间延伸的类型漂移区域1的部分引入肖特基接触来形成反向漏电流和导通电压，形成肖特基路口。

4. 发明授权

US07157785B2 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US07157785B2
公开(公告)日：2007-01-02
申请号：US10928927
申请日：2004-08-27
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L27/85 , H01L27/102 , H01L29/70 , H01L31/11 , H01L31/07
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了制造半导体器件的方法。反向阻断IGBT通过将p型基极区域和发射极电极之间延伸的类型漂移区域1的部分引入肖特基接触来形成反向漏电流和导通电压，形成肖特基路口。

5. 发明申请

US20060186508A1 Reverse blocking semiconductor device and a method for manufacturing the same 有权
公开(公告)号：US20060186508A1
公开(公告)日：2006-08-24
申请号：US11397478
申请日：2006-04-04
申请人： Michio Nemoto , Manabu Takei , Tatsuya Naito
发明人： Michio Nemoto , Manabu Takei , Tatsuya Naito
IPC分类号： H01L23/58
CPC分类号： H01L29/0646 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/404 , H01L29/7395
摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

6. 发明授权

US07638368B2 Reverse blocking semiconductor device and a method for manufacturing the same 有权
标题翻译：反向阻挡半导体器件及其制造方法
公开(公告)号：US07638368B2
公开(公告)日：2009-12-29
申请号：US11843152
申请日：2007-08-22
申请人： Michio Nemoto , Manabu Takei , Tatsuya Naito
发明人： Michio Nemoto , Manabu Takei , Tatsuya Naito
IPC分类号： H01L2/1332
CPC分类号： H01L29/0646 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/404 , H01L29/7395
摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.
摘要翻译：没有显示隔离区域对反向恢复峰值电流的不利影响的反向阻挡半导体器件，其具有显示令人满意的软恢复的击穿耐受结构，其抑制基本上伴随常规反向阻断IGBT的反向漏电流的恶化，并且公开了令人满意的低导通电压。该器件包括形成在n漂移层上的MOS栅极结构，该MOS栅极结构包括形成在该漂移层的前表面区域中的p +基极层，形成在该基极层的表面区域中的n +发射极区域，覆盖发射极区域和漂移层之间的基底层的表面区域的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。发射极电极与MOS栅极结构的发射极区域和基极层接触。 p +隔离区域通过漂移层包围MOS栅极结构，并延伸穿过漂移层的整个厚度。 p +集电极层形成在漂移层的后表面上并连接到隔离区的后侧。距离W大于厚度d，其中距离W是距离发射电极的一部分的最外侧位置（与基层接触的部分）到隔离区域的最内位置的距离，以及厚度d是漂移层的深度方向的尺寸。

7. 发明授权

US07049674B2 Reverse blocking semiconductor device and a method for manufacturing the same 有权
公开(公告)号：US07049674B2
公开(公告)日：2006-05-23
申请号：US10822643
申请日：2004-04-12
申请人： Michio Nemoto , Manabu Takei , Tatsuya Naito
发明人： Michio Nemoto , Manabu Takei , Tatsuya Naito
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/0646 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/404 , H01L29/7395
摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

8. 发明申请

US20130075819A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130075819A1
公开(公告)日：2013-03-28
申请号：US13640481
申请日：2012-01-16
申请人： Manabu Takei , Yusuke Kobayashi
发明人： Manabu Takei , Yusuke Kobayashi
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/78 , H01L21/02107 , H01L29/0619 , H01L29/0661 , H01L29/404 , H01L29/66348 , H01L29/7395
摘要： A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.
摘要翻译：半导体器件包括用于主电流的有源部分和击穿电压的击穿部分。外周边部围绕n型半导体衬底的一个主表面上的有源部分。击穿承受部具有环形半导体突起，其具有在其四个角中的每一个中包括弯曲部分的矩形平面图案作为保护环。该环状半导体突起在其中具有p型区域，夹在比p型区域更深的多个凹部之间，并且在其表面上具有跨绝缘膜的导电膜。因此，可以以低成本制造在窄宽度下获得高击穿电压的击穿耐受结构，即使在场的图案化处理存在变化的情况下，击穿电压几乎没有下降氧化膜。

9. 发明授权

US08269760B2 Pixel driving device, light emitting device, and property parameter acquisition method in a pixel driving device 有权
标题翻译：像素驱动装置，发光装置和像素驱动装置中的特性参数获取方法
公开(公告)号：US08269760B2
公开(公告)日：2012-09-18
申请号：US12626747
申请日：2009-11-27
申请人： Jun Ogura , Manabu Takei , Shunji Kashiyama
发明人： Jun Ogura , Manabu Takei , Shunji Kashiyama
IPC分类号： G06F3/038
CPC分类号： G09G3/3291 , G09G2300/0819 , G09G2300/0842 , G09G2320/04
摘要： A pixel driving device has a voltage impressing circuit that outputs a reference voltage that exceeds a threshold voltage of a drive transistor, a voltage measurement circuit, and a property parameter acquisition circuit that acquires a property parameter related to an electronic property of a pixel. The pixel driving device impresses the reference voltage on the pixel that has a light emitting element and the drive transistor. The voltage measurement circuit acquires voltage of a signal line, as measured voltages, after each of a plurality of the settling times elapsing from the time when the reference voltage is cut. The property parameter acquisition circuit acquires, as property parameters, the threshold voltage and a current amplification factor of drive transistor based on values of a plurality of measured voltages acquired by the voltage measurement circuit.
摘要翻译：像素驱动装置具有输出超过驱动晶体管的阈值电压的参考电压的电压施加电路，电压测量电路和获取与像素的电子特性相关的特性参数的属性参数获取电路。像素驱动装置对具有发光元件的像素和驱动晶体管施加参考电压。在从基准电压切断时起经过的多个稳定时间的每一个之后，电压测量电路获取作为测量电压的信号线的电压。属性参数获取电路基于由电压测量电路获取的多个测量电压的值作为特性参数获取驱动晶体管的阈值电压和电流放大系数。

10. 发明授权

US08269759B2 Pixel driving device, light emitting device, and property parameter acquisition method in a pixel driving device 有权
标题翻译：像素驱动装置，发光装置，以及像素驱动装置中的特性参数获取方法
公开(公告)号：US08269759B2
公开(公告)日：2012-09-18
申请号：US12626731
申请日：2009-11-27
申请人： Jun Ogura , Manabu Takei , Shunji Kashiyama
发明人： Jun Ogura , Manabu Takei , Shunji Kashiyama
IPC分类号： G06F3/038
CPC分类号： G09G3/3291 , G09G3/3233 , G09G2300/0842 , G09G2320/043
摘要： A pixel driving device in which, after a reference voltage exceeds a threshold voltage of a drive transistor is impressed through the signal lines on each pixel equipping a light emitting element and the drive transistor, set the signal lines in a state of high impedance, and acquires a voltage value of one end of the signal lines subsequent to a predetermined settling time elapsing, and acquires the threshold voltage of the drive transistor for each pixel and the current amplification factor of the pixel drive circuit as a first property parameter based on acquired voltage values at the time a plurality of first settling times longer than a predetermined value and acquires an irregularity parameter indicating the irregularity in the current amplification factor based on the value of the first property parameter and the measured voltage value acquired at the time shorter than the predetermined value.
摘要翻译：一种像素驱动装置，其中，在参考电压超过驱动晶体管的阈值电压的情况下，通过装配发光元件和驱动晶体管的每个像素上的信号线施加脉冲，将信号线设置为高阻抗状态，以及获取在经过预定的建立时间之后的信号线的一端的电压值，并且基于获取的电压获取每个像素的驱动晶体管的阈值电压和像素驱动电路的当前放大系数作为第一属性参数在多个第一建立时间比预定值多的时间值，并且基于第一属性参数的值和在比预定时间短的时间获取的测量电压值来获取指示当前放大因子的不规则性的不规则参数值。

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