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    • 1. 发明授权
    • Driving method for improving display uniformity in multiplexed pixel
    • 提高复用像素显示均匀性的驱动方法
    • US07221352B2
    • 2007-05-22
    • US10892785
    • 2004-07-15
    • Manabu KodateKai SchleupenEisuke Kanzaki
    • Manabu KodateKai SchleupenEisuke Kanzaki
    • G09G3/36G09G3/30G02F1/136
    • G02F1/136286G02F1/13624G09G3/3659G09G2300/0814G09G2310/0205G09G2310/0251G09G2320/0219
    • Disclosed is an image display device to secure uniformity of a screen without luminance unevenness by reducing the number of signal lines and enhancing accuracy in voltages to be applied to respective pixels. In an interval after a scan line Gn+2 is set to selection potential until the scan line Gn+2 is set to non-selection potential, a first display signal having first electric potential to be given to a pixel electrode A is supplied to a signal line, whereby the pixel electrode A and a pixel electrode B are provided with the first electric potential. In addition, after the scan line Gn+2 is set to the non-selection potential, a second display signal having second electric potential to be given to the pixel electrode B is supplied to the signal line, whereby the pixel electrode B is provided with the second electric potential. In this event, a variation of compensative potential for offsetting a difference between an electric potential variation corresponding to parasitic capacitance between the pixel electrode A and scan lines Gn+1 and Gn+2, and an electric potential variation corresponding to parasitic capacitance between the pixel electrode B and the scan line Gn+1, is given to the scan lines Gn+1 and Gn+2 for compensation.
    • 公开了一种图像显示装置,通过减少信号线的数量并提高施加到各个像素的电压的精度来确保屏幕的均匀性,而没有亮度不均匀。 在将扫描线Gn + 2设定为选择电位直到扫描线Gn + 2被设置为非选择电位的间隔之后,将具有给予像素电极A的第一电位的第一显示信号提供给 信号线,由此像素电极A和像素电极B被设置有第一电位。 此外,在将扫描线Gn + 2设定为非选择电位之后,将具有给予像素电极B的第二电位的第二显示信号提供给信号线,由此像素电极B设置有 第二个电位。 在这种情况下,用于抵消与像素电极A和扫描线Gn + 1和Gn + 2之间的寄生电容相对应的电位变化之间的差异的补偿电位的变化以及与像素电极A之间的寄生电容相对应的电位变化 电极B和扫描线Gn + 1被赋予扫描线Gn + 1和Gn + 2进行补偿。
    • 4. 发明授权
    • Circuit device for controlling circuit components connected in series or
in a matrix-like network
    • 用于控制串联或矩阵状网络中连接的电路组件的电路装置
    • US5517543A
    • 1996-05-14
    • US207758
    • 1994-03-08
    • Kai SchleupenErnst Luder
    • Kai SchleupenErnst Luder
    • G09G3/36G11C19/18G11C19/28
    • G09G3/3685G09G3/3674G11C19/184G09G2310/0286
    • The circuit device has a plurality of cascaded stages. Each cascaded stage includes several partial stages and has at most two capacitors (C.sub.n1, C.sub.nB) and at most seven transistors (T.sub.n1, T.sub.n2, T.sub.n3, T.sub.n4, T.sub.n5, T.sub.n6, T.sub.n7). The circuit device includes a device for controlling the cascaded stages with four periodic clock signals (.PHI..sub.1, .PHI..sub.2, .PHI..sub.3, .sub.101 .sub.4) phase-shifted about 90.degree. relative to each other such that each of the cascaded stages is controlled by a respective assigned one of four predetermined sets of two of the four periodic clock signals and the same one of the four predetermined set repeats every fifth cascaded stage. Each cascaded stage includes an output stage (12, 12') including a bootstrap-capacitor (C.sub.nB) and three transistors (T.sub.n5, T.sub.n6, T.sub.n7) electrically connected to the bootstrap-capacitor (C.sub.nB); and a charging and discharging stage (11) for the bootstrap-capacitor (C.sub.nB). The charging and discharging stage (11) includes at least one transistor (T.sub.n4) connected electrically to the bootstrap capacitor (C.sub.nB). Each cascaded stage can advantageously also include an inverter stage connected to the charging and discharging stage and including two transistors (T.sub.n1, T.sub.n2) and a memory capacitor (C.sub.n1) electrically connected with each other and controlled by an input signal so that so that both transistors (T.sub.n1, T.sub.n2) are never simultaneously conducting.
    • 电路装置具有多个级联级。 每个级联级包括几个部分级,并且具有至多两个电容器(Cn1,CnB)和至多七个晶体管(Tn1,Tn2,Tn3,Tn4,Tn5,Tn6,Tn7)。 该电路装置包括用于通过相对于彼此相移大约90度的四个周期性时钟信号(PHI 1,PHI 2,PHI 3,101 4)来控制级联级的装置,使得每个级联级由 在四个周期性时钟信号中的四个预定组中的四个预定集合中的每一个分配一个,并且每五个级联阶段中四个预定集合重复中的相同一个。 每个级联级包括电连接到自举电容器(CnB)的包括自举电容器(CnB)和三个晶体管(Tn5,Tn6,Tn7)的输出级(12,12'); 以及用于自举电容器(CnB)的充电和放电级(11)。 充电和放电级(11)包括至少一个与自举电容器(CnB)电连接的晶体管(Tn4)。 每个级联级可以有利地还包括连接到充电和放电级的反相器级并且包括彼此电连接并由输入信号控制的两个晶体管(Tn1,Tn2)和存储电容器(Cn1),使得两个晶体管 (Tn1,Tn2)从不同时导通。